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1. 发明授权

US07027307B2 Clock routing in multiple channel modules and bus systems 失效
公开(公告)号：US07027307B2
公开(公告)日：2006-04-11
申请号：US10420308
申请日：2003-04-22
申请人： Ravindranath T. Kollipara , David Nguyen , Belgacem Haba
发明人： Ravindranath T. Kollipara , David Nguyen , Belgacem Haba
IPC分类号： H05K7/02 , H05K7/06 , H05K7/08
CPC分类号： G11C5/04 , G06F13/409 , G11C5/00 , H05K1/023 , H05K1/117 , H05K1/141 , H05K1/147 , H05K1/148 , H05K7/1459 , H05K2201/10189
摘要： An apparatus is provided, which includes a memory interface circuit, a clock signal generating circuit, and a plurality of memory circuits. The memory circuits are operatively coupled and arranged in an order on a plurality of memory modules, such that the memory module positioned at the beginning of the order is coupled to an output of the clock signal generating circuit and the memory interface circuit. The memory module that is positioned at the end of the order is unique in that it includes a clock signal terminating circuit connected to the last memory integrated circuit. With this configuration, a clock loop is formed by directly routing the clock signal from the output of the clock signal generating circuit through each of the memory modules in the order (without connecting to any of the intervening memory integrated circuits) to the memory integrated circuit positioned at the end of the order. Then, the clock signal is asserted on the previous memory modules by routing it back through the memory integrated circuits thereon, in reverse order to the memory integrated circuit positioned at the beginning of the order and from there to the memory interface circuit. To complete the clock loop, the clock signal is again asserted by routing it from the memory interface circuit back through the memory integrated circuits in order to the memory integrated circuit positioned at the end of the order. Finally, the clock signal is terminated at the clock signal terminating circuit on the memory module positioned at the end of the order.

2. 发明申请

US20120001670A1 Clock Routing in Mulitiple Channel Modules and Bus Systems 审中-公开
标题翻译：多通道模块和总线系统中的时钟路由
公开(公告)号：US20120001670A1
公开(公告)日：2012-01-05
申请号：US13235251
申请日：2011-09-16
申请人： Ravindranath T. Kollipara , David Nguyen , Belgacem Haba
发明人： Ravindranath T. Kollipara , David Nguyen , Belgacem Haba
IPC分类号： G06F1/04
CPC分类号： G11C5/04 , G06F13/409 , G11C5/00 , H05K1/023 , H05K1/117 , H05K1/141 , H05K1/147 , H05K1/148 , H05K7/1459 , H05K2201/10189
摘要： The terminating module includes integrated circuits and a termination circuit which receive clock signals from the integrated circuit. The integrated circuit includes at least one memory integrated circuit mounted on a printed circuit board. An electrical connector is configured to couple the terminating module to a motherboard. Additionally, the termination circuit includes a resistor. In another embodiment, the terminating module provides a printed circuit board, a memory integrated circuit mounted on the circuit board, a terminator circuit which includes a resistor, and an electrical connector. The electrical connector couples the terminating module to a motherboard.
摘要翻译：终端模块包括集成电路和从集成电路接收时钟信号的终端电路。集成电路包括安装在印刷电路板上的至少一个存储器集成电路。电连接器被配置为将终端模块耦合到主板。另外，终端电路包括电阻器。在另一个实施例中，端接模块提供印刷电路板，安装在电路板上的存储器集成电路，包括电阻器和电连接器的终端电路。电连接器将终端模块耦合到主板。

3. 发明授权

US08050042B2 Clock routing in multiple channel modules and bus systems and method for routing the same 失效
标题翻译：多通道模块和总线系统中的时钟路由及其路由方法
公开(公告)号：US08050042B2
公开(公告)日：2011-11-01
申请号：US11190561
申请日：2005-07-26
申请人： Ravindranath T. Kollipara , David Nguyen , Belgacem Haba
发明人： Ravindranath T. Kollipara , David Nguyen , Belgacem Haba
IPC分类号： H05K7/02 , H05K7/06 , H05K7/08 , H05K7/10
CPC分类号： G11C5/04 , G06F13/409 , G11C5/00 , H05K1/023 , H05K1/117 , H05K1/141 , H05K1/147 , H05K1/148 , H05K7/1459 , H05K2201/10189
摘要： The terminating module and method include integrated circuits and a termination circuit which receive clock signals from the integrated circuit. The integrated circuit includes at least one memory integrated circuit mounted on a printed circuit board. An electrical connector is configured to couple the terminating module to a motherboard. Additionally, the termination circuit includes a resistor. In another embodiment, the terminating module provides a printed circuit board, a memory integrated circuit mounted on the circuit board, a terminator circuit which includes a resistor, and an electrical connector. The electrical connector couples the terminating module to a motherboard.
摘要翻译：终端模块和方法包括集成电路和从集成电路接收时钟信号的终端电路。集成电路包括安装在印刷电路板上的至少一个存储器集成电路。电连接器被配置为将终端模块耦合到主板。另外，终端电路包括电阻器。在另一个实施例中，端接模块提供印刷电路板，安装在电路板上的存储器集成电路，包括电阻器和电连接器的终端电路。电连接器将终端模块耦合到主板。

4. 发明授权

US06590781B2 Clock routing in multiple channel modules and bus systems 失效
标题翻译：多通道模块和总线系统中的时钟路由
公开(公告)号：US06590781B2
公开(公告)日：2003-07-08
申请号：US09817828
申请日：2001-03-26
申请人： Ravindranath T. Kollipara , David Nguyen , Belgacem Haba
发明人： Ravindranath T. Kollipara , David Nguyen , Belgacem Haba
IPC分类号： H05K702
CPC分类号： G11C5/04 , G06F13/409 , G11C5/00 , H05K1/023 , H05K1/117 , H05K1/141 , H05K1/147 , H05K1/148 , H05K7/1459 , H05K2201/10189
摘要： An apparatus is provided, which includes a memory interface circuit, a clock signal generating circuit, and a plurality of memory circuits. The memory circuits are operatively coupled and arranged in an order on a plurality of memory modules, such that the memory module positioned at the beginning of the order is coupled to an output of the clock signal generating circuit and the memory interface circuit. The memory module that is positioned at the end of the order is unique in that it includes a clock signal terminating circuit connected to the last memory integrated circuit. With this configuration, a clock loop is formed by directly routing the clock signal from the output of the clock signal generating circuit through each of the memory modules in the order (without connecting to any of the intervening memory integrated circuits) to the memory integrated circuit positioned at the end of the order. Then, the clock signal is asserted on the previous memory modules by routing it back through the memory integrated circuits thereon, in reverse order to the memory integrated circuit positioned at the beginning of the order and from there to the memory interface circuit. To complete the clock loop, the clock signal is again asserted by routing it from the memory interface circuit back through the memory integrated circuits in order to the memory integrated circuit positioned at the end of the order. Finally, the clock signal is terminated at the clock signal terminating circuit on the memory module positioned at the end of the order.
摘要翻译：提供了一种装置，其包括存储器接口电路，时钟信号发生电路和多个存储器电路。存储器电路被可操作地耦合并按照多个存储器模块的顺序排列，使得位于该命令开始处的存储器模块被耦合到时钟信号发生电路和存储器接口电路的输出端。定位在订单结尾的存储器模块是唯一的，因为它包括连接到最后存储器集成电路的时钟信号终端电路。利用这种配置，通过将时钟信号发生电路的输出的时钟信号通过每个存储器模块以顺序（不连接到任何中间存储器集成电路）直接路由到存储器集成电路而形成时钟环路定位在订单结束。然后，时钟信号在先前的存储器模块上通过其上的存储器集成电路将其重新布置，以与定位在订单开始处的存储器集成电路相反，并且从那里到存储器接口电路。为了完成时钟环路，时钟信号通过将存储器接口电路从存储器集成电路重新路由到存储器集成电路定位在订单结束处而被再次断言。最后，时钟信号终止在位于订单结束的存储器模块上的时钟信号终端电路。

5. 发明授权

US07285443B2 Stacked semiconductor module 有权
标题翻译：堆叠式半导体模块
公开(公告)号：US07285443B2
公开(公告)日：2007-10-23
申请号：US11378008
申请日：2006-03-16
申请人： Thomas F. Fox , Sayeh Khalili , Belgacem Haba , David Nguyen , Richard Warmke , Xingchao Yuan
发明人： Thomas F. Fox , Sayeh Khalili , Belgacem Haba , David Nguyen , Richard Warmke , Xingchao Yuan
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： G11C5/02 , G11C5/04 , G11C29/08 , G11C2029/4402 , H01L23/5382 , H01L25/0657 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor module is provided that includes a semiconductor housing and a plurality of integrated circuit dice positioned within the housing. The semiconductor module also includes a programmable memory device positioned within the housing and electrically coupled to the plurality of integrated circuit dice. The programmable memory device is programmable to identify the integrated circuit dice that meet a predetermined standard, such as an operating frequency requirement, or a core timing grade. Further, a method is provided for accessing a semiconductor module. The above mentioned housing is provided to enclose the plurality of integrated circuit dice and the programmable memory device. The integrated circuit dice of the plurality of integrated circuit dice that meet a predetermined standard are then identified. The programmable memory device is subsequently programmed to identify the selected integrated circuit dice.
摘要翻译：提供了半导体模块，其包括半导体外壳和位于壳体内的多个集成电路芯片。半导体模块还包括位于壳体内的电可耦合到多个集成电路芯片的可编程存储器件。可编程存储器件可编程以识别满足预定标准（例如工作频率要求或核心定时等级）的集成电路芯片。此外，提供了一种用于访问半导体模块的方法。提供上述壳体以包围多个集成电路芯片和可编程存储器件。然后识别满足预定标准的多个集成电路芯片的集成电路芯片。随后编程可编程存储器件以识别所选择的集成电路芯片。

6. 发明授权

US07037757B2 Stacked semiconductor module 失效
公开(公告)号：US07037757B2
公开(公告)日：2006-05-02
申请号：US10783822
申请日：2004-02-20
申请人： Thomas F. Fox , Sayeh Khalili , Belgacem Haba , David Nguyen , Richard Warmke , Xingchao Yuan
发明人： Thomas F. Fox , Sayeh Khalili , Belgacem Haba , David Nguyen , Richard Warmke , Xingchao Yuan
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： G11C5/02 , G11C5/04 , G11C29/08 , G11C2029/4402 , H01L23/5382 , H01L25/0657 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor module is provided that includes a semiconductor housing and a plurality of integrated circuit dice positioned within the housing. The semiconductor module also includes a programmable memory device positioned within the housing and electrically coupled to the plurality of integrated circuit dice. The programmable memory device is programmable to identify the integrated circuit dice that meet a predetermined standard, such as an operating frequency requirement, or a core timing grade. Further, a method is provided for accessing a semiconductor module. The above mentioned housing is provided to enclose the plurality of integrated circuit dice and the programmable memory device. The integrated circuit dice of the plurality of integrated circuit dice that meet a predetermined standard are then identified. The programmable memory device is subsequently programmed to identify the selected integrated circuit dice.

7. 发明申请

US20050254221A1 Clock routing in multiple channel modules and bus systems 失效
标题翻译：多通道模块和总线系统中的时钟路由
公开(公告)号：US20050254221A1
公开(公告)日：2005-11-17
申请号：US11190561
申请日：2005-07-26
申请人： Ravindranath Kollipara , David Nguyen , Belgacem Haba
发明人： Ravindranath Kollipara , David Nguyen , Belgacem Haba
IPC分类号： G06F13/40 , G11C5/00 , H05K1/02 , H05K1/11 , H05K1/14 , H05K7/06 , H05K7/14
CPC分类号： G11C5/04 , G06F13/409 , G11C5/00 , H05K1/023 , H05K1/117 , H05K1/141 , H05K1/147 , H05K1/148 , H05K7/1459 , H05K2201/10189
摘要： The terminating module includes integrated circuits and a termination circuit which receive clock signals from the integrated circuit. The integrated circuit includes at least one memory integrated circuit mounted on a printed circuit board. An electrical connector is configured to couple the terminating module to a motherboard. Additionally, the termination circuit includes a resistor. In another embodiment, the terminating module provides a printed circuit board, a memory integrated circuit mounted on the circuit board, a terminator circuit which includes a resistor, and an electrical connector. The electrical connector couples the terminating module to a motherboard
摘要翻译：终端模块包括集成电路和从集成电路接收时钟信号的终端电路。集成电路包括安装在印刷电路板上的至少一个存储器集成电路。电连接器被配置为将终端模块耦合到主板。另外，终端电路包括电阻器。在另一个实施例中，端接模块提供印刷电路板，安装在电路板上的存储器集成电路，包括电阻器和电连接器的终端电路。电连接器将终端模块耦合到主板

8. 发明授权

US06898085B2 Multiple channel modules and bus systems using same 失效
公开(公告)号：US06898085B2
公开(公告)日：2005-05-24
申请号：US10695854
申请日：2003-10-30
申请人： Belgacem Haba , Richard E. Perego , David Nguyen , Billy W. Garrett, Jr. , Ely Tsern , Craig E. Hampel , Wai-Yeung Yip
发明人： Belgacem Haba , Richard E. Perego , David Nguyen , Billy W. Garrett, Jr. , Ely Tsern , Craig E. Hampel , Wai-Yeung Yip
IPC分类号： G06F13/40 , G11C5/00 , H05K1/02 , H05K1/11 , H05K1/14 , H05K7/06 , H05K7/14 , H05K7/02 , H05K7/10
CPC分类号： G11C5/04 , G06F13/409 , G11C5/00 , H05K1/023 , H05K1/117 , H05K1/141 , H05K1/147 , H05K1/148 , H05K7/1459 , H05K2201/10189
摘要： Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.

9. 发明申请

US20060160271A1 Stacked semiconductor module 有权
公开(公告)号：US20060160271A1
公开(公告)日：2006-07-20
申请号：US11378008
申请日：2006-03-16
申请人： Thomas Fox , Sayeh Khalili , Belgacem Haba , David Nguyen , Richard Warmke , Xingchao Yuan
发明人： Thomas Fox , Sayeh Khalili , Belgacem Haba , David Nguyen , Richard Warmke , Xingchao Yuan
IPC分类号： H01L21/50
CPC分类号： G11C5/02 , G11C5/04 , G11C29/08 , G11C2029/4402 , H01L23/5382 , H01L25/0657 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor module is provided that includes a semiconductor housing and a plurality of integrated circuit dice positioned within the housing. The semiconductor module also includes a programmable memory device positioned within the housing and electrically coupled to the plurality of integrated circuit dice. The programmable memory device is programmable to identify the integrated circuit dice that meet a predetermined standard, such as an operating frequency requirement, or a core timing grade. Further, a method is provided for accessing a semiconductor module. The above mentioned housing is provided to enclose the plurality of integrated circuit dice and the programmable memory device. The integrated circuit dice of the plurality of integrated circuit dice that meet a predetermined standard are then identified. The programmable memory device is subsequently programmed to identify the selected integrated circuit dice.

10. 发明授权

US07170314B2 Multiple channel modules and bus systems using same 失效
标题翻译：多通道模块和使用相同的总线系统
公开(公告)号：US07170314B2
公开(公告)日：2007-01-30
申请号：US11054955
申请日：2005-02-11
申请人： Belgacem Haba , Richard E. Perego , David Nguyen , Billy W. Garrett, Jr. , Ely Tsern , Crag E. Hampel , Wai-Yeng Yip
发明人： Belgacem Haba , Richard E. Perego , David Nguyen , Billy W. Garrett, Jr. , Ely Tsern , Crag E. Hampel , Wai-Yeng Yip
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： G11C5/04 , G06F13/409 , G11C5/00 , H05K1/023 , H05K1/117 , H05K1/141 , H05K1/147 , H05K1/148 , H05K7/1459 , H05K2201/10189
摘要： Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.
摘要翻译：公开了可用于实现具有1至N个信道的模块的各种模块结构。总线系统可以通过这种模块的互连形成。

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