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1. 发明授权

US4080589A Error density detector 失效
标题翻译：误差密度检测器
公开(公告)号：US4080589A
公开(公告)日：1978-03-21
申请号：US583147
申请日：1975-06-02
申请人： Ralph LeRoy Kline
发明人： Ralph LeRoy Kline
IPC分类号： G01R23/15 , H03K5/19 , H03K5/18
CPC分类号： G01R23/15 , H03K5/19
摘要： An initial error indicated by a pulse at the binary input is applied through a gating circuit to trigger a monostable multivibrator (one-shot) to start a timing interval. The output of the one-shot is applied to a second gating circuit which inhibits the first gating circuit to prevent retriggering of the one-shot. Subsequent error pulses are then applied directly to a counting mechanism which counts the errors which occur during the predetermined time interval established by the one-shot. An acceptable error density is established by the predetermined time interval for the one-shot in relation to the number of errors that would occur during this predetermined time interval. If the number of errors which occur exceeds the acceptable error density, the counting circuit puts out a signal which may be applied to an alarm (or framing) circuit. Once the error counter produces an output, i.e., exceeds the acceptable error density, the counter applies a binary indication to the second gating circuit which causes the first gating circuit to retrigger the one-shot. Further, each error pulse which occurs before the one-shot times out will now trigger the one-shot. In order for the circuit to reset, an error-free period, equal to the period of the one-shot, must occur.
摘要翻译：由二进制输入端的脉冲指示的初始误差通过门控电路施加，以触发单稳态多谐振荡器（单稳态）以开始定时间隔。一次性的输出被施加到第二门控电路，其阻止第一门控电路防止单触发的重新触发。然后将随后的误差脉冲直接施加到计数机构，该计数机构对由单次拍摄建立的预定时间间隔期间发生的误差进行计数。相对于在该预定时间间隔内将发生的错误数量，针对单触发的预定时间间隔建立可接受的误差密度。如果出现的错误数超过可接受的误差密度，则计数电路会输出可能应用于报警（或成帧）电路的信号。一旦错误计数器产生输出，即超过可接受的误差密度，则计数器向第二选通电路施加二进制指示，使得第一门控电路重新触发单触发。此外，在单次超时之前发生的每个错误脉冲现在将触发一次。为了使电路复位，必须发生等于单次触发周期的无错误周期。

2. 发明授权

US4010325A Framing circuit for digital signals using evenly spaced alternating framing bits 失效
标题翻译：使用偶数间隔替代框架的数字信号的框架电路
公开(公告)号：US4010325A
公开(公告)日：1977-03-01
申请号：US627323
申请日：1975-10-30
申请人： Ralph LeRoy Kline
发明人： Ralph LeRoy Kline
IPC分类号： H04J3/06 , H04J3/07 , H04J3/12
CPC分类号： H04J3/073 , H04J3/0617 , H04J3/125
摘要： In a digital multiplexer which employs pulse stuffing and a plurality of signaling bits including evenly spaced framing bits, a framing circuit consists essentially of a pair of flip-flops which store the last values of a winking framing signal or the error signal which may have occurred during the framing time slots. Outputs of the flip-flops are connected to gating circuits. One said gate produces an output signal when an error occurs. This error signal is applied to an error density detector. When an out-of-frame condition occurs, i.e., the receiving circuit is considered not to be synchronized with the transmitting circuit, the error density detector output which is applied to a clock pulse generator causes an extended count to occur for each error occurrence. This offsets the bit stream by one time slot for each error following the out-of-frame condition, and this extended count follows the extended count due to the presence of a signaling bit. A control bit generator operates under the control of the reconstructed clock signal, the clock pulse generator, the sample counter, and the framing circuit. When the out-of-frame condition causes an extended count, the control bit generator does not advance. However, the error is cleared by the end of the first time slot following the second extended count. If the winking framing signal is "in frame", the extra count is inhibited. The framing and/or reframing process is accomplished more readily by means of a preview circuit which consists of an additional flip-flop and two additional gates. The flip-flop stores the last value of the bit following the control bit. If the winking framing signal is out of frame and an error occurs, the counters in the control bit clock generator are shifted such that the bit in the additional flip-flop is now the previous framing bit. Thus, the next framing bit must be the opposite to be correct. The additional gates are used to reset or preset the control bit generator so that a predetermined framing bit will be made available to compare with the incoming framing signal.

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