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1. 发明申请

US20060047990A1 System and method for data storage and transfer between two clock domains 审中-公开
标题翻译：两个时钟域之间的数据存储和传输的系统和方法
公开(公告)号：US20060047990A1
公开(公告)日：2006-03-02
申请号：US10933074
申请日：2004-09-01
申请人： Ralph James , Douglas Larson
发明人： Ralph James , Douglas Larson
IPC分类号： G06F1/12
CPC分类号： G06F1/12
摘要： In a memory hub system, several daisy-chained memory hubs are connected to a single memory controller. The memory hub transmitters and receivers operate in a high-speed clock domain, while the logic cores of the memory hubs operate in a low-speed clock domain. A clock domain interface advantageously provides data storage and transfer between the two clock domains without stalling the logic in the low-speed clock domain and without interrupting data movement in the high-speed clock domain.
摘要翻译：在存储器集线器系统中，几个菊花链存储器集线器连接到单个存储器控制器。存储器集线器发射器和接收器以高速时钟域工作，而存储器集线器的逻辑核心以低速时钟域工作。时钟域接口有利地在两个时钟域之间提供数据存储和传输，而不会使低速时钟域中的逻辑失速，而不会中断高速时钟域中的数据移动。

2. 发明授权

US07257683B2 Memory arbitration system and method having an arbitration packet protocol 有权
公开(公告)号：US07257683B2
公开(公告)日：2007-08-14
申请号：US10809839
申请日：2004-03-24
申请人： Joseph M. Jeddeloh , Ralph James
发明人： Joseph M. Jeddeloh , Ralph James
IPC分类号： G06F12/00
CPC分类号： G06F13/1642 , G06F13/1605 , G06F13/1684
摘要： A memory hub and method for transmitting a read response on a data path of a memory hub interposed between a transmitting memory hub and a receiving memory hub. An arbitration packet including data indicative of a data path configuration for an associated read response is received at the memory hub. The arbitration packet is decoded, and the data path is configured in accordance with the data of the arbitration packet. The associated read response is received at the memory hub and the associated read response is coupled to the configured data path for transmitting the same to the receiving memory hub.

3. 发明申请

US20060271720A1 System and method for transmitting data packets in a computer system having a memory hub architecture 有权
公开(公告)号：US20060271720A1
公开(公告)日：2006-11-30
申请号：US11432017
申请日：2006-05-10
申请人： Ralph James , Joe Jeddeloh
发明人： Ralph James , Joe Jeddeloh
IPC分类号： G06F13/36
CPC分类号： G06F13/1642
摘要： A system and method for transmitting data packets from a memory hub to a memory controller is disclosed. The system includes an upstream reception port coupled an upstream link. The upstream reception port receives the data packets from downstream memory hubs. The system further includes a bypass bus coupled to the upstream reception port. The bypass bus transports the data packets from the upstream reception port. The system further includes a temporary storage coupled to the upstream reception port and configured to receive the data packets from the upstream reception port. The system further includes a bypass multiplexer for selectively coupling an upstream transmission port to either one of a core logic circuit, the temporary storage, or the bypass bus. The system further includes a breakpoint logic circuit coupled to the bypass multiplexer and configured to switch the bypass multiplexer to selectively connect the upstream transmission port to either one of the core logic circuit, the bypass bus, or the temporary storage. The system further includes a local memory coupled to the core logic circuit and operable to receive and send the data packets to the core logic circuit.

4. 发明授权

US07133991B2 Method and system for capturing and bypassing memory transactions in a hub-based memory system 有权
公开(公告)号：US07133991B2
公开(公告)日：2006-11-07
申请号：US10645288
申请日：2003-08-20
申请人： Ralph James
发明人： Ralph James
IPC分类号： G06F13/00
CPC分类号： G06F13/4256 , G11C7/10
摘要： A memory hub includes a reception interface that receives data words and captures the data words in response to a first clock signal in a first time domain. The interface also provides groups of the captured data words on an output in response to a second clock signal in a second time domain. A transmission interface is coupled to the reception interface to receive the captured data words and captures the data words in response to a third clock signal in the first time domain. This interface provides the captured data words on an output. Local control circuitry is coupled to the output of the reception interface to receive the groups of data words and develops memory requests corresponding to the groups of data words. The first clock domain is defined by clock signals having frequencies higher than frequencies of clock signals in the second clock domain.

5. 发明申请

US20060218331A1 System and method for communicating the synchronization status of memory modules during initialization of the memory modules 有权
标题翻译：用于在存储器模块初始化期间传送存储器模块的同步状态的系统和方法
公开(公告)号：US20060218331A1
公开(公告)日：2006-09-28
申请号：US11432018
申请日：2006-05-10
申请人： Ralph James
发明人： Ralph James
IPC分类号： G06F13/14
CPC分类号： G06F13/1684
摘要： A memory system includes a memory hub controller coupled to a plurality of memory modules each of which includes a memory hub. The memory hub controller and the memory hubs each include at least one receiver that is synchronized to an internal clock signal during initialization. The memory hub controller and the memory hubs each transmit an initialization complete signal downstream when at least one receiver in the controller or hub is initialized and, in the case of the memory hubs, when a downstream initialization signal has also been received. Similarly, the memory hubs transmit an initialization signal upstream to another memory hub or the controller when both of its receivers are initialized and an upstream initialization signal has also been received. Receipt of an upstream initialization signal by the memory hub controller signifies that all of the receivers have been initialized.
摘要翻译：存储器系统包括耦合到多个存储器模块的存储器集线器控制器，每个存储器模块包括存储器集线器。存储器集线器控制器和存储器集线器各自包括在初始化期间与内部时钟信号同步的至少一个接收器。当控制器或集线器中的至少一个接收器被初始化时，存储器集线器控制器和存储器集线器都向下发送初始化完成信号，并且在存储器集线器的情况下，当还接收到下游初始化信号时。类似地，当其两个接收机被初始化并且还接收到上游初始化信号时，存储器集线器向上游发送初始化信号到另一个存储集线器或控制器。由存储器集线器控制器接收上游初始化信号表示所有接收器已被初始化。

6. 发明申请

US20120066461A1 MEMORY ARBITRATION SYSTEM AND METHOD HAVING AN ARBITRATION PACKET PROTOCOL 有权
标题翻译：存在仲裁系统和具有仲裁分组协议的方法
公开(公告)号：US20120066461A1
公开(公告)日：2012-03-15
申请号：US13301653
申请日：2011-11-21
申请人： Joseph M. Jeddeloh , Ralph James
发明人： Joseph M. Jeddeloh , Ralph James
IPC分类号： G06F12/00
CPC分类号： G06F13/1642 , G06F13/1605 , G06F13/1684
摘要： A memory hub and method for transmitting a read response on a data path of a memory hub interposed between a transmitting memory hub and a receiving memory hub. An arbitration packet including data indicative of a data path configuration for an associated read response is received at the memory hub. The arbitration packet is decoded, and the data path is configured in accordance with the data of the arbitration packet. The associated read response is received at the memory hub and the associated read response is coupled to the configured data path for transmitting the same to the receiving memory hub.
摘要翻译：一种用于在插入在发送存储器集线器和接收存储器集线器之间的存储器集线器的数据路径上发送读取响应的存储集线器和方法。在存储器集线器处接收包括指示相关联的读取响应的数据路径配置的数据的仲裁分组。仲裁分组被解码，并且根据仲裁分组的数据来配置数据路径。在存储器集线器处接收相关联的读取响应，并且将相关联的读取响应耦合到所配置的数据路径，以将其发送到接收存储器集线器。

7. 发明授权

US08082404B2 Memory arbitration system and method having an arbitration packet protocol 有权
标题翻译：具有仲裁分组协议的存储器仲裁系统和方法
公开(公告)号：US08082404B2
公开(公告)日：2011-12-20
申请号：US12169493
申请日：2008-07-08
申请人： Joseph M. Jeddeloh , Ralph James
发明人： Joseph M. Jeddeloh , Ralph James
IPC分类号： G06F12/00
CPC分类号： G06F13/1642 , G06F13/1605 , G06F13/1684
摘要： A memory hub and method for transmitting a read response on a data path of a memory hub interposed between a transmitting memory hub and a receiving memory hub. An arbitration packet including data indicative of a data path configuration for an associated read response is received at the memory hub. The arbitration packet is decoded, and the data path is configured in accordance with the data of the arbitration packet. The associated read response is received at the memory hub and the associated read response is coupled to the configured data path for transmitting the same to the receiving memory hub.
摘要翻译：一种用于在插入在发送存储器集线器和接收存储器集线器之间的存储器集线器的数据路径上发送读取响应的存储集线器和方法。在存储器集线器处接收包括指示相关联的读取响应的数据路径配置的数据的仲裁分组。仲裁分组被解码，并且根据仲裁分组的数据来配置数据路径。在存储器集线器处接收相关联的读取响应，并且将相关联的读取响应耦合到所配置的数据路径，以将其发送到接收存储器集线器。

8. 发明申请

US20110191517A1 SYSTEM AND METHOD FOR TRANSMITTING DATA PACKETS IN A COMPUTER SYSTEM HAVING A MEMORY HUB ARCHITECTURE 有权
标题翻译：在具有存储器架构的计算机系统中传输数据包的系统和方法
公开(公告)号：US20110191517A1
公开(公告)日：2011-08-04
申请号：US13088227
申请日：2011-04-15
申请人： Ralph James , Joe Jeddeloh
发明人： Ralph James , Joe Jeddeloh
IPC分类号： G06F13/36
CPC分类号： G06F13/1642
摘要： A system and method for transmitting data packets from a memory hub to a memory controller is disclosed. The system includes an upstream reception port coupled to an upstream link. The upstream reception port receives the data packets from downstream memory hubs. The system further includes a bypass bus coupled to the upstream reception port. The bypass bus transports the data packets from the upstream reception port. The system further includes a temporary storage coupled to the upstream reception port and configured to receive the data packets from the upstream reception port. The system further includes a bypass multiplexer for selectively coupling an upstream transmission port to either one of a core logic circuit, the temporary storage, or the bypass bus. The system further includes a breakpoint logic circuit coupled to the bypass multiplexer and configured to switch the bypass multiplexer to selectively connect the upstream transmission port to either one of the core logic circuit, the bypass bus, or the temporary storage. The system further includes a local memory coupled to the core logic circuit and operable to receive and send the data packets to the core logic circuit.
摘要翻译：公开了一种用于将数据分组从存储器集线器传输到存储器控制器的系统和方法。该系统包括耦合到上游链路的上游接收端口。上游接收端口从下游存储器集线器接收数据包。该系统还包括耦合到上游接收端口的旁路总线。旁路总线传输来自上游接收端口的数据包。该系统还包括耦合到上游接收端口并被配置为从上游接收端口接收数据分组的临时存储器。该系统还包括旁路多路复用器，用于将上游传输端口选择性地耦合到核心逻辑电路，临时存储器或旁路总线中的任一个。所述系统还包括耦合到所述旁路多路复用器的断点逻辑电路，并且被配置为切换旁路多路复用器以选择性地将上游传输端口连接到核心逻辑电路，旁路总线或临时存储器中的任一个。该系统还包括耦合到核心逻辑电路并可操作以将数据分组接收并发送到核心逻辑电路的本地存储器。

9. 发明授权

US07461286B2 System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding 有权
标题翻译：在没有时钟转发的情况下，使用学习序列建立高速非同步接口的通信的系统和方法
公开(公告)号：US07461286B2
公开(公告)日：2008-12-02
申请号：US11433181
申请日：2006-05-11
申请人： Ralph James
发明人： Ralph James
IPC分类号： G06F1/04
CPC分类号： G06F13/4243 , Y10S370/905
摘要： A memory system includes a memory hub controller that sends write data to a plurality of memory modules through a downstream data bus and receives read data from the memory modules through an upstream data bus. The memory hub controller includes a receiver coupled to the upstream data bus and a transmitter coupled to the downstream data bus. Similarly, each of the memory modules includes a receiver coupled to the downstream data bus and a transmitter coupled to the upstream data bus. Each receiver includes a receive clock generator that is synchronized by coupling a known pattern of data to the receiver. The receiver determines which phase of the receive clock best captures the known pattern and uses that receive clock phase during normal operation.
摘要翻译：存储器系统包括存储器集线器控制器，其通过下游数据总线向多个存储器模块发送写入数据，并通过上游数据总线从存储器模块接收读取数据。存储器集线器控制器包括耦合到上游数据总线的接收器和耦合到下行数据总线的发送器。类似地，每个存储器模块包括耦合到下游数据总线的接收器和耦合到上游数据总线的发送器。每个接收机包括通过将已知模式的数据耦合到接收器来同步的接收时钟发生器。接收机确定接收时钟的哪个相位最佳地捕获已知模式，并在正常操作期间使用该接收时钟相位。

10. 发明申请

US20080294856A1 MEMORY ARBITRATION SYSTEM AND METHOD HAVING AN ARBITRATION PACKET PROTOCOL 有权
标题翻译：存在仲裁系统和具有仲裁分组协议的方法
公开(公告)号：US20080294856A1
公开(公告)日：2008-11-27
申请号：US12169493
申请日：2008-07-08
申请人： Joseph M. Jeddeloh , Ralph James
发明人： Joseph M. Jeddeloh , Ralph James
IPC分类号： G06F12/00
CPC分类号： G06F13/1642 , G06F13/1605 , G06F13/1684
摘要： A memory hub and method for transmitting a read response on a data path of a memory hub interposed between a transmitting memory hub and a receiving memory hub. An arbitration packet including data indicative of a data path configuration for an associated read response is received at the memory hub. The arbitration packet is decoded, and the data path is configured in accordance with the data of the arbitration packet. The associated read response is received at the memory hub and the associated read response is coupled to the configured data path for transmitting the same to the receiving memory hub.
摘要翻译：一种用于在插入在发送存储器集线器和接收存储器集线器之间的存储器集线器的数据路径上发送读取响应的存储集线器和方法。在存储器集线器处接收包括指示相关联的读取响应的数据路径配置的数据的仲裁分组。仲裁分组被解码，并且根据仲裁分组的数据来配置数据路径。在存储器集线器处接收相关联的读取响应，并且将相关联的读取响应耦合到所配置的数据路径，以将其发送到接收存储器集线器。

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