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1. 发明授权

US09312848B2 Glitch suppression in an amplifier 有权
标题翻译：放大器中的毛刺抑制
公开(公告)号：US09312848B2
公开(公告)日：2016-04-12
申请号：US14511800
申请日：2014-10-10
申请人： QUALCOMM Incorporated
发明人： Xinwang Zhang , Vijayakumar Dhanasekaran , Le Wang , Ankit Srivastava
IPC分类号： H03K3/00 , H03K17/16 , H03F1/26
CPC分类号： H03K17/161 , H03F1/26 , H03F2200/372 , H03K17/167 , H03K2217/0072
摘要： A driver circuit includes detectors responsive to the operating region that a driven switch is operating in. The driver circuit is operative to drive the gate of the driven switch at a speed responsive to the output of the detectors.
摘要翻译：驱动器电路包括响应于操作区域的检测器，驱动开关正在操作。驱动器电路用于以响应于检测器的输出的速度驱动从动开关的门。

2. 发明申请

US20150349710A1 RC OSCILLATOR BASED ON DELAY-FREE COMPARATOR 有权
标题翻译： RC振荡器基于无延迟比较器
公开(公告)号：US20150349710A1
公开(公告)日：2015-12-03
申请号：US14290665
申请日：2014-05-29
申请人： QUALCOMM INCORPORATED
发明人： Le Wang , Arash Mehrabi
IPC分类号： H03B5/04 , H03B5/20
CPC分类号： H03B5/04 , H03B5/20 , H03K3/0231 , H03K3/30 , H03K4/50 , H04B5/04
摘要： Cancelling a delay in a comparator of an RC oscillator configured to generate a clock pulse, including: selectively coupling a plurality of current sources to a first capacitor, a second capacitor, and a resistor, wherein the plurality of current source charge and discharge the first capacitor and the second capacitor, and charge the resistor; charging the first capacitor at a higher rate during a first phase of the clock pulse than a second phase of the clock pulse, and charging the second capacitor at a higher rate during a third phase of the clock pulse than a fourth phase of the clock pulse; and generating the clock pulse by enabling the comparator to compare a voltage on the first or second capacitor with a voltage on the resistor.
摘要翻译：取消被配置为产生时钟脉冲的RC振荡器的比较器中的延迟，包括：选择性地将多个电流源耦合到第一电容器，第二电容器和电阻器，其中所述多个电流源对第一电容器和第二电容器，并对电阻充电; 在时钟脉冲的第一相位期间以比时钟脉冲的第二相位更高的速率对第一电容器充电，并且在时钟脉冲的第三相位期间以比时钟脉冲的第四相位更高的速率对第二电容器充电 ; 并通过使比较器将第一或第二电容器上的电压与电阻器上的电压进行比较来产生时钟脉冲。

3. 发明授权

US09385649B2 RC oscillator based on delay-free comparator 有权
标题翻译： RC振荡器基于无延迟比较器
公开(公告)号：US09385649B2
公开(公告)日：2016-07-05
申请号：US14290665
申请日：2014-05-29
申请人： QUALCOMM INCORPORATED
发明人： Le Wang , Arash Mehrabi
IPC分类号： H03K3/26 , H03B5/04 , H03B5/20 , H04B5/04 , H03K3/30 , H03K3/0231 , H03K4/50
CPC分类号： H03B5/04 , H03B5/20 , H03K3/0231 , H03K3/30 , H03K4/50 , H04B5/04
摘要： Cancelling a delay in a comparator of an RC oscillator configured to generate a clock pulse, including: selectively coupling a plurality of current sources to a first capacitor, a second capacitor, and a resistor, wherein the plurality of current source charge and discharge the first capacitor and the second capacitor, and charge the resistor; charging the first capacitor at a higher rate during a first phase of the clock pulse than a second phase of the clock pulse, and charging the second capacitor at a higher rate during a third phase of the clock pulse than a fourth phase of the clock pulse; and generating the clock pulse by enabling the comparator to compare a voltage on the first or second capacitor with a voltage on the resistor.
摘要翻译：取消被配置为产生时钟脉冲的RC振荡器的比较器中的延迟，包括：选择性地将多个电流源耦合到第一电容器，第二电容器和电阻器，其中所述多个电流源对第一电容器和第二电容器，并对电阻充电; 在时钟脉冲的第一相位期间以比时钟脉冲的第二相位更高的速率对第一电容器充电，并且在时钟脉冲的第三相位期间以比时钟脉冲的第四相位更高的速率对第二电容器充电 ; 并通过使比较器将第一或第二电容器上的电压与电阻器上的电压进行比较来产生时钟脉冲。

4. 发明申请

US20150304137A1 TRANSMISSION GATE FOR BIAS VOLTAGE GENERATION 审中-公开
标题翻译：用于偏置电压发生的变速箱
公开(公告)号：US20150304137A1
公开(公告)日：2015-10-22
申请号：US14257425
申请日：2014-04-21
申请人： QUALCOMM Incorporated
发明人： Meysam Azin , Wenchang Huang , Le Wang
IPC分类号： H04L25/08 , H04L27/04
CPC分类号： H04L25/0276 , H03F3/245 , H03F3/45475 , H03F2203/45514 , H03K5/2481 , H03K17/063 , H04L25/0272
摘要： An apparatus includes a transmission gate configured to generate a signal based on a first differential input signal and a second differential input signal. The apparatus further includes biasing circuitry responsive to the transmission gate and configured to output a bias voltage based on the signal.
摘要翻译：一种装置包括：传输门，被配置为基于第一差分输入信号和第二差分输入信号产生信号。该装置还包括响应于传输门并被配置为基于该信号输出偏置电压的偏置电路。

5. 发明申请

US20140103897A1 GLITCH SUPPRESSION IN DC-TO-DC POWER CONVERSION 审中-公开
标题翻译：直流到直流电源转换中的GLITCH抑制
公开(公告)号：US20140103897A1
公开(公告)日：2014-04-17
申请号：US13654341
申请日：2012-10-17
申请人： QUALCOMM INCORPORATED
发明人： Le Wang , Xiaohong Quan , Vijayakumar Dhanasekaran , Omid Shoaei
IPC分类号： G05F3/08
CPC分类号： H02M3/07 , H02M1/38 , H02M2001/0029 , H03K17/162 , H03K17/164
摘要： Exemplary embodiments are directed to devices and method for operating a charge pump. A method may include activating a first switch coupled between a capacitor and a ground voltage over a first period of a charging phase. The first period may coincide with a non-overlapping time between the charging phase and an output phase. The method may also include activating a second switch coupled between the capacitor and an input voltage over a second period of the charging phase, wherein the first period begins prior to the second period. Further, the method may include deactivating the second switch over a third period of the charging phase and deactivating the first switch over a fourth period of the charging phase, wherein the third period begins prior to the fourth period.
摘要翻译：示例性实施例涉及用于操作电荷泵的装置和方法。一种方法可以包括在充电阶段的第一周期上激活耦合在电容器和接地电压之间的第一开关。第一周期可以与充电阶段和输出阶段之间的非重叠时间重合。该方法还可以包括在充电阶段的第二周期内激活耦合在电容器和输入电压之间的第二开关，其中第一周期在第二周期之前开始。此外，该方法可以包括在充电阶段的第三周期内去激活第二开关，并且在充电阶段的第四周期上去激活第一开关，其中第三周期在第四周期之前开始。

6. 发明申请

US20160306382A1 CONTROL CIRCUITS FOR GENERATING OUTPUT ENABLE SIGNALS, AND RELATED SYSTEMS AND METHODS 有权
标题翻译：用于产生输出使能信号的控制电路及相关系统和方法
公开(公告)号：US20160306382A1
公开(公告)日：2016-10-20
申请号：US14713058
申请日：2015-05-15
申请人： QUALCOMM Incorporated
发明人： Lior Amarilio , Meysam Azin , Alexander Khazin , Le Wang
IPC分类号： G06F1/10 , G06F1/06
CPC分类号： G06F1/10 , G06F1/06 , G06F13/4291
摘要： Control circuits for generating output enable signals are disclosed. In one aspect, a control circuit is provided that employs combinatorial logic to generate an output enable signal that meets timing constraints using a standard clock signal, a feedback clock signal based on the standard clock signal, and a single data rate (SDR) data output stream. The control circuit includes a double data rate (DDR) conversion circuit configured to generate a DDR output stream based on a received SDR output stream. The control circuit includes an output enable circuit configured to receive the standard clock signal, feedback clock signal, and DDR output stream, and to generate the output enable signal that is asserted and de-asserted according to the defined timing constraints. The control circuit is configured to generate an accurately timed output enable signal without the need for a fast clock signal in addition to the standard clock signal.
摘要翻译：公开了用于产生输出使能信号的控制电路。在一个方面，提供了一种控制电路，其采用组合逻辑来产生使用标准时钟信号满足定时约束的输出使能信号，基于标准时钟信号的反馈时钟信号和单个数据速率（SDR）数据输出流。控制电路包括双数据速率（DDR）转换电路，配置为基于接收到的SDR输出流生成DDR输出流。控制电路包括输出使能电路，其被配置为接收标准时钟信号，反馈时钟信号和DDR输出流，并且根据定义的时序约束生成被断言和解除断言的输出使能信号。控制电路被配置为产生精确定时的输出使能信号，而不需要除了标准时钟信号之外的快速时钟信号。

7. 发明申请

US20150381161A1 GLITCH SUPPRESSION IN AN AMPLIFIER 有权
标题翻译：放大器中的GLITCH抑制
公开(公告)号：US20150381161A1
公开(公告)日：2015-12-31
申请号：US14511800
申请日：2014-10-10
申请人： QUALCOMM Incorporated
发明人： Xinwang Zhang , Vijayakumar Dhanasekaran , Le Wang , Ankit Srivastava
IPC分类号： H03K17/16 , H03F1/26
CPC分类号： H03K17/161 , H03F1/26 , H03F2200/372 , H03K17/167 , H03K2217/0072
摘要： A driver circuit includes detectors responsive to the operating region that a driven switch is operating in. The driver circuit is operative to drive the gate of the driven switch at a speed responsive to the output of the detectors.
摘要翻译：驱动器电路包括响应于操作区域的检测器，驱动开关正在操作。驱动器电路用于以响应于检测器的输出的速度驱动从动开关的门。

8. 发明授权

US09658645B2 Control circuits for generating output enable signals, and related systems and methods 有权
公开(公告)号：US09658645B2
公开(公告)日：2017-05-23
申请号：US14713058
申请日：2015-05-15
申请人： QUALCOMM Incorporated
发明人： Lior Amarilio , Meysam Azin , Alexander Khazin , Le Wang
IPC分类号： G06F1/00 , G06F1/10 , G06F13/42 , G06F1/06
CPC分类号： G06F1/10 , G06F1/06 , G06F13/4291
摘要： Control circuits for generating output enable signals are disclosed. In one aspect, a control circuit is provided that employs combinatorial logic to generate an output enable signal that meets timing constraints using a standard clock signal, a feedback clock signal based on the standard clock signal, and a single data rate (SDR) data output stream. The control circuit includes a double data rate (DDR) conversion circuit configured to generate a DDR output stream based on a received SDR output stream. The control circuit includes an output enable circuit configured to receive the standard clock signal, feedback clock signal, and DDR output stream, and to generate the output enable signal that is asserted and de-asserted according to the defined timing constraints. The control circuit is configured to generate an accurately timed output enable signal without the need for a fast clock signal in addition to the standard clock signal.

9. 发明授权

US09312755B2 Charge pump power savings 有权
标题翻译：充电泵省电
公开(公告)号：US09312755B2
公开(公告)日：2016-04-12
申请号：US13785601
申请日：2013-03-05
申请人： QUALCOMM Incorporated
发明人： Le Wang , Vijayakumar Dhanasekaran
IPC分类号： H03B1/00 , H03K3/00 , H02M3/07
CPC分类号： H02M3/07 , H02M2003/071
摘要： Exemplary embodiments are directed to systems, devices, methods, and computer-readable media for reducing static and dynamic power consumption of a charge pump. In one embodiment, a device may include a plurality of switches, each switch of the plurality having a gate coupled to a dedicated driver of a plurality of drivers. The device may further include at least one clamp switch coupled to at least one driver of the plurality of drivers and configured to adjust a rail voltage of the at least one driver if an input voltage is greater than a threshold voltage. In another embodiment, the device may include a plurality of multiplexers, each multiplexer of the plurality of multiplexers coupled to a portion of an associated switch of the plurality of switches and configured to disable the portion of the associated switch if a clock frequency of the charge pump is below a threshold frequency.
摘要翻译：示例性实施例涉及用于减少电荷泵的静态和动态功耗的系统，设备，方法和计算机可读介质。在一个实施例中，设备可以包括多个开关，多个开关中的每个开关具有耦合到多个驱动器的专用驱动器的栅极。该装置还可以包括耦合到多个驱动器中的至少一个驱动器的至少一个钳位开关，并被配置为如果输入电压大于阈值电压则调整至少一个驱动器的轨道电压。在另一个实施例中，设备可以包括多个多路复用器，多个复用器的每个多路复用器耦合到多个交换机中的相关联的开关的一部分，并且被配置为如果电荷的时钟频率泵低于阈值频率。

10. 发明申请

US20140253180A1 CHARGE PUMP POWER SAVINGS 有权
标题翻译：充电泵节电
公开(公告)号：US20140253180A1
公开(公告)日：2014-09-11
申请号：US13785601
申请日：2013-03-05
申请人： QUALCOMM INCORPORATED
发明人： Le Wang , Vijayakumar Dhanasekaran
IPC分类号： H03K3/012
CPC分类号： H02M3/07 , H02M2003/071
摘要： Exemplary embodiments are directed to systems, devices, methods, and computer-readable media for reducing static and dynamic power consumption of a charge pump. In one embodiment, a device may include a plurality of switches, each switch of the plurality having a gate coupled to a dedicated driver of a plurality of drivers. The device may further include at least one clamp switch coupled to at least one driver of the plurality of drivers and configured to adjust a rail voltage of the at least one driver if an input voltage is greater than a threshold voltage. In another embodiment, the device may include a plurality of multiplexers, each multiplexer of the plurality of multiplexers coupled to a portion of an associated switch of the plurality of switches and configured to disable the portion of the associated switch if a clock frequency of the charge pump is below a threshold frequency.
摘要翻译：示例性实施例涉及用于减少电荷泵的静态和动态功耗的系统，设备，方法和计算机可读介质。在一个实施例中，设备可以包括多个开关，多个开关中的每个开关具有耦合到多个驱动器的专用驱动器的栅极。该装置还可以包括耦合到多个驱动器中的至少一个驱动器的至少一个钳位开关，并被配置为如果输入电压大于阈值电压则调整至少一个驱动器的轨道电压。在另一个实施例中，设备可以包括多个多路复用器，多个复用器的每个多路复用器耦合到多个交换机中的相关联的开关的一部分，并且被配置为如果电荷的时钟频率泵低于阈值频率。

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