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1. 发明授权

US6094376A Data output buffer control circuit for a semiconductor memory device 失效
标题翻译：用于半导体存储器件的数据输出缓冲器控制电路
公开(公告)号：US6094376A
公开(公告)日：2000-07-25
申请号：US998287
申请日：1997-12-24
申请人： Pil-Soon Park , Kyung-Woo Kang , Soo-In Cho
发明人： Pil-Soon Park , Kyung-Woo Kang , Soo-In Cho
IPC分类号： G11C11/417 , G11C7/10 , G11C11/401 , G11C11/407 , G11C11/409 , G11C16/04
CPC分类号： G11C7/1051
摘要： A data output buffer control circuit for a semiconductor memory device assures a column address setup time and a valid data setup time in EDO mode by eliminating short glitches in the data output buffer. The circuit assures the column address setup time by disabling the data output buffer for a predetermined period of time after an address transition, regardless of the state of a column address strobe signal. The circuit assures the setup time for valid data by sensing when the address is set up relative to when the column address strobe signal is activated, and then enabling the data output buffer so as to maintain invalid data in the data output buffer long enough to prevent a short glitch in the data output buffer if the column address is set up before the column address strobe signal is activated. The circuit includes a pulse generator for generating a pulse signal each time it senses a column address transition, and a latch circuit for combining the pulse signal with the column address strobe signal so as to generate a buffer control signal for enabling and disabling the data output buffer.
摘要翻译：用于半导体存储器件的数据输出缓冲器控制电路通过消除数据输出缓冲器中的短毛刺来确保EDO模式下的列地址建立时间和有效的数据建立时间。该电路通过在地址转换之后的预定时间段禁用数据输出缓冲器来确保列地址建立时间，而不管列地址选通信号的状态如何。电路通过检测地址是否相对于列地址选通信号被激活而设置的时间来保证有效数据的建立时间，然后启用数据输出缓冲器，以便在数据输出缓冲器中保持足够长的时间以防止如果在列地址选通信号被激活之前设置了列地址，则数据输出缓冲器中的短暂毛刺。电路包括用于每次检测列地址转换时产生脉冲信号的脉冲发生器和用于将脉冲信号与列地址选通信号组合的锁存电路，以便产生用于启用和禁用数据输出的缓冲器控制信号缓冲。

2. 发明授权

US5299168A Circuit for detecting refresh address signals of a semiconductor memory device 失效
标题翻译：用于检测半导体存储器件的刷新地址信号的电路
公开(公告)号：US5299168A
公开(公告)日：1994-03-29
申请号：US50780
申请日：1993-04-22
申请人： Kyung-Woo Kang
发明人： Kyung-Woo Kang
IPC分类号： G11C11/401 , G11C11/406 , G11C29/00 , G11C29/02 , G11C29/08 , G11C29/12 , G11C7/00
CPC分类号： G11C29/02 , G11C11/406
摘要： Disclosed is a refresh address test circuit of a semiconductor memory device having a self-refresh function using a plurality of internal refresh address signals, comprising a plurality of the address test paths, each including a first sub-path which receives an initial logic level of one bit of an initial refresh address and a second sub-path of which receives successive corresponding bits of said refresh address, a plurality of comparators, each connected to the first sub-path and the second sub-path, a test output circuit receives the output signals generated from the plurality of comparators to determine whether a complete cycle of refresh addresses have been generated.
摘要翻译：公开了一种具有使用多个内部刷新地址信号的自刷新功能的半导体存储器件的刷新地址测试电路，包括多个地址测试路径，每个地址测试路径包括接收初始逻辑电平的第一子路径初始刷新地址的一位和其第二子路径接收所述刷新地址的连续对应位，多个比较器，每个比较器连接到第一子路径和第二子路径，测试输出电路接收从多个比较器产生的输出信号，以确定是否已经产生了刷新地址的完整周期。

3. 发明授权

US06285611B1 Memory device having input and output sense amplifiers that occupy less circuit area 有权
标题翻译：具有输入和输出读出放大器的存储器件占用较少的电路面积
公开(公告)号：US06285611B1
公开(公告)日：2001-09-04
申请号：US09596331
申请日：2000-06-16
申请人： Kyung-Woo Kang
发明人： Kyung-Woo Kang
IPC分类号： G11C700
CPC分类号： G11C7/065 , G11C11/4091 , G11C2207/063
摘要： A memory device includes a plurality of memory banks, a plurality of data line pairs coupled to the memory banks, and an input/output (IO) sense amplifier shared by at least two neighboring memory banks. The IO sense amplifier includes a plurality of current sense amplifiers and a latch sense amplifier. Each current sense amplifier couples to and senses a corresponding data line pair. The latch sense amplifier selectively senses signals from the plurality of current sense amplifiers and generates an output signal at a suitable voltage for peripheral circuitry. Circuit area required for sense amplifiers is reduced because at least two memory banks share a latch sense amplifier, instead of having one latch sense amplifier for each memory bank.
摘要翻译：存储器件包括多个存储体，耦合到存储体的多个数据线对以及由至少两个相邻存储体共享的输入/输出（IO）读出放大器。 IO读出放大器包括多个电流检测放大器和锁存读出放大器。每个电流检测放大器耦合到并感测相应的数据线对。锁存读出放大器有选择地感测来自多个电流检测放大器的信号，并产生用于外围电路的合适电压的输出信号。读出放大器所需的电路面积减少，因为至少两个存储体共享一个锁存读出放大器，而不是为每个存储体组提供一个锁存读出放大器。

4. 发明授权

US06847567B2 Sense amplifier drive circuits responsive to predecoded column addresses and methods for operating the same 有权
标题翻译：感测放大器驱动电路响应于预编码列地址及其操作方法
公开(公告)号：US06847567B2
公开(公告)日：2005-01-25
申请号：US10361320
申请日：2003-02-10
申请人： Kyung-Woo Kang
发明人： Kyung-Woo Kang
IPC分类号： G11C7/06 , G11C7/08 , G11C7/18 , G11C11/4091 , G11C11/4097 , G11C7/00
CPC分类号： G11C7/06 , G11C7/18 , G11C11/4091 , G11C11/4097 , G11C2207/065
摘要： Sense amplifier drive circuits drive a sense amplifier in a semiconductor (integrated circuit) memory device. A sense amplifier drive signal generator is configured to generate a sense amplifier drive signal responsive to at least one predecoded column address received at an input thereof. The sense amplifier drive signal generator may receive predecoded column addresses from a column predecoder. A delay circuit coupled to the sense amplifier drive signal generator may delay the sense amplifier drive signal by a selected time and output a delayed sense amplifier drive signal for driving the sense amplifier. The selected time may be based on a time from activation of a bit line selection signal of the semiconductor (integrated circuit) memory device to application of selected data to the sense amplifier. Corresponding methods are also provided.
摘要翻译：感测放大器驱动电路驱动半导体（集成电路）存储器件中的读出放大器。读出放大器驱动信号发生器被配置为响应于在其输入处接收的至少一个预解码列地址产生读出放大器驱动信号。读出放大器驱动信号发生器可以从列预解码器接收预编码的列地址。耦合到读出放大器驱动信号发生器的延迟电路可以将读出放大器驱动信号延迟选定的时间并输出用于驱动读出放大器的延迟读出放大器驱动信号。所选择的时间可以基于从激活半导体（集成电路）存储器件的位线选择信号到将所选择的数据应用于读出放大器的时间。还提供了相应的方法。

5. 发明授权

US5566116A Bit line sense amplifier of semiconductor memory device 失效
标题翻译：半导体存储器件的位线读出放大器
公开(公告)号：US5566116A
公开(公告)日：1996-10-15
申请号：US492578
申请日：1995-06-20
申请人： Kyung-Woo Kang
发明人： Kyung-Woo Kang
IPC分类号： H01L27/04 , G11C11/4091 , G11C7/00
CPC分类号： G11C11/4091
摘要： A bit line sense amplifier in a semiconductor memory device having a sense amplifier for sensing and amplifying a logic slate of data stored in a selected memory cell in response to a row address and for outputting sense-amplified data to a bit line pair, and transmission means for transmitting output data of the bit line pair to the corresponding input/output line pair thereto. The bit line sense amplifier includes a secondary power supply voltage generating circuit for supplying a secondary power supply voltage and a secondary ground potential in response to a block selection signal for selecting a memory block including the selected memory cell, and a secondary sense amplifier being supplied with the secondary power supply voltage and secondary ground potential, and for converting data indicative of a potential difference of the bit line pair and input/output line pair to a level of the secondary power supply voltage and ground potential in response to the column selection signal.
摘要翻译：一种半导体存储器件中的位线读出放大器，具有读出放大器，用于响应于行地址检测和放大存储在所选存储单元中的数据的逻辑位数，并将读出放大数据输出到位线对，以及传输用于将位线对的输出数据发送到对应的输入/输出线对的装置。位线读出放大器包括辅助电源电压产生电路，用于响应于用于选择包括所选择的存储单元的存储块的块选择信号，以及提供辅助电源电压和二次接地电位具有次级电源电压和次级接地电位，并且用于将表示位线对和输入/输出线对的电位差的数据响应于列选择信号转换为二次电源电压和接地电位的电平。

6. 发明授权

US06826108B2 Integrated circuit memory device power supply circuits and methods of operating same 失效
公开(公告)号：US06826108B2
公开(公告)日：2004-11-30
申请号：US10279896
申请日：2002-10-24
申请人： Kyung-Woo Kang
发明人： Kyung-Woo Kang
IPC分类号： G11C700
CPC分类号： G11C5/147
摘要： Integrated circuit devices include a control circuit that selectively drive a power supply terminal of a memory cell array and a sense amplifier of the integrated circuit device with a first power supply voltage and/or a second power supply voltage responsive to a control signal. The second power supply voltage is delivered to the integrated circuit device separate from the first power supply voltage. The integrated circuit device may further include an internal voltage generator circuit powered by an external power supply separate from the second power supply voltage and the first power supply voltage may be an internal voltage generated by the internal voltage generator circuit. The integrated circuit device may also include a data output circuit that is powered by the second power supply voltage. Corresponding methods are also provided.

7. 发明授权

US5737276A Memory device with fast extended data out (EDO) mode and methods of operation therefor 失效
标题翻译：具有快速扩展数据输出（EDO）模式的存储器件及其操作方法
公开(公告)号：US5737276A
公开(公告)日：1998-04-07
申请号：US712499
申请日：1996-09-11
申请人： Sang-Gil Shin , Kyung-Woo Kang
发明人： Sang-Gil Shin , Kyung-Woo Kang
IPC分类号： G11C11/409 , G11C7/10 , G11C11/34 , G11C11/401 , G11C11/407 , G11C8/00
CPC分类号： G11C7/106 , G11C7/1051
摘要： A memory device having normal and extended data out (EDO). modes includes an array of memory cells arranged in plurality of rows and columns, first and second data latches which store data, a column address input which receives a column address signal, and a column address strobe input which receives a column address strobe signal. First latch control means, responsive to said column address input and to the column address strobe input, electrically couples one memory cell in the array of memory cells and the first data latch when a column address signal is asserted at the column address input and electrically decouples the one memory cell and the first data latch when a column address strobe signal is asserted at the column address strobe input, thereby latching data present in the one memory cell prior to assertion of the column address strobe signal in the first data latch. Second latch control means, responsive to the column address strobe input, electrically couples the first data latch and the second data latch when a column address strobe signal is asserted at the column address strobe input and electrically decouples the first data latch and the second data latch when a column address strobe signal is deasserted at the column address strobe input, thereby latching data present in the first data latch prior to deassertion of the column address strobe signal in the second data latch.
摘要翻译：具有正常和扩展数据输出（EDO）的存储器件。模式包括排列成多个行和列的存储单元的阵列，存储数据的第一和第二数据锁存器，接收列地址信号的列地址输入和接收列地址选通信号的列地址选通输入。当列地址信号在列地址输入处被断言时，响应于所述列地址输入和列地址选通输入的第一锁存控制装置将存储单元阵列和第一数据锁存器中的一个存储单元电耦合一个存储单元和第一数据锁存器，当列地址选通信号在列地址选通输入端被断言时，从而在第一数据锁存器中断言列地址选通信号之前锁存存在于一个存储单元中的数据。当列列地址选通信号在列地址选通输入处断言时，响应于列地址选通输入的第二锁存器控制装置电耦合第一数据锁存器和第二数据锁存器，并且电分离第一数据锁存器和第二数据锁存器当列地址选通信号在列地址选通输入端被置为无效时，从而在第二数据锁存器中的列地址选通信号的取消取消之前锁存存在于第一数据锁存器中的数据。

8. 发明授权

US5410262A Data output buffer of a semiconductor integrated circuit 失效
标题翻译：半导体集成电路的数据输出缓冲器
公开(公告)号：US5410262A
公开(公告)日：1995-04-25
申请号：US255780
申请日：1994-06-08
申请人： Kyung-Woo Kang
发明人： Kyung-Woo Kang
IPC分类号： G11C11/417 , G11C11/409 , G11C16/06 , G11C17/00 , G11C17/18 , H01L21/822 , H01L27/04 , H03K17/16 , H03K19/003 , H03K3/09
CPC分类号： H03K17/164
摘要： A data output buffer of a semiconductor integrated circuit is operable in response to data input to data lines and comprises a first pull-down control circuit which generates a first pull-down signal in response to the data input to the data lines. A second pull-down control circuit generates a second pull-down signal in response to the data input to the data lines, the second pull-down signal being generated at a predetermined time after the first pull-down signal is generated and causing the first pull down signal to be deactivated. A first pull-down transistor shares an output node with a pull-up transistor and is responsive to the first pull-down signal to pull-down a predetermined amount of voltage at the output node. A second pull-down transistor is responsive to the second pull down signal for pulling down a residual amount of voltage at the output node.
摘要翻译：半导体集成电路的数据输出缓冲器可响应于输入到数据线的数据而工作，并且包括第一下拉控制电路，其响应于输入到数据线的数据产生第一下拉信号。第二下拉控制电路响应于输入到数据线的数据产生第二下拉信号，在第一下拉信号产生之后的预定时间产生第二下拉信号，并且使第一下拉信号下拉信号被禁用。第一下拉晶体管与上拉晶体管共享输出节点，并响应于第一下拉信号在输出节点下拉预定量的电压。第二下拉晶体管响应于第二下拉信号来降低输出节点处的剩余电压量。

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