专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060106991A1 Victim prefetching in a cache hierarchy 失效
标题翻译：受害者在缓存层次结构中预取
公开(公告)号：US20060106991A1
公开(公告)日：2006-05-18
申请号：US10989997
申请日：2004-11-16
申请人： Peter Franaszek , Steven Kunkel , Luis Lastras Montano , Aaron Sawdey
发明人： Peter Franaszek , Steven Kunkel , Luis Lastras Montano , Aaron Sawdey
IPC分类号： G06F12/00
CPC分类号： G06F12/122 , G06F12/0862 , G06F12/0897
摘要： We present a “directory extension” (hereinafter “DX”) to aid in prefetching between proximate levels in a cache hierarchy. The DX may maintain (1) a list of pages which contains recently ejected lines from a given level in the cache hierarchy, and (2) for each page in this list, the identity of a set of ejected lines, provided these lines are prefetchable from, for example, the next level of the cache hierarchy. Given a cache fault to a line within a page in this list, other lines from this page may then be prefetched without the substantial overhead to directory lookup which would otherwise be required.
摘要翻译：我们提出一个“目录扩展名”（以下简称“DX”）来辅助缓存层级中的邻近级别之间的预取。 DX可以维护（1）包含最近从缓存层级中的给定级别排出的行的页面列表，以及（2）对于该列表中的每个页面，提供这些行是可预取的集合的标识从例如缓存层次结构的下一级。给定列表中页面内的行的高速缓存错误，然后可以预取此页面中的其他行，而不需要大量开销，否则将需要目录查找。

2. 发明授权

US07334088B2 Page descriptors for prefetching and memory management 失效
标题翻译：页面描述符用于预取和内存管理
公开(公告)号：US07334088B2
公开(公告)日：2008-02-19
申请号：US10326634
申请日：2002-12-20
申请人： Peter Franaszek
发明人： Peter Franaszek
IPC分类号： G06F12/00 , G06F15/00
CPC分类号： G06F12/0862 , G06F2212/6022 , G06F2212/6024
摘要： A computer system and a method for enhancing the cache prefetch behavior. A computer system including a processor, a main memory, a prefetch controller, a cache memory, a prefetch buffer, and a main memory, wherein each page in the main memory has associated with it a tag, which is used for controling the prefetching of a variable subset of lines from this page as well as lines from at least one other page. And, coupled to the processor is a prefetch controller, wherein the prefetch controller responds to the processor determining a fault (or miss) occurred to a line of data by fetching a corresponding line of data with the corresponding tag, with the corresponding tag to be stored in the prefetch buffer, and sending the corresponding line of data to the cache memory.
摘要翻译：一种用于增强缓存预取行为的计算机系统和方法。一种包括处理器，主存储器，预取控制器，高速缓冲存储器，预取缓冲器和主存储器的计算机系统，其中主存储器中的每个页面与其相关联，该标签用于控制预取来自该页面的行的可变子集以及至少一个其他页面的行。并且，耦合到处理器的是预取控制器，其中预取控制器响应于处理器确定一行数据发生的故障（或未命中），通过相应的标签获取相应的数据行，相应的标签为存储在预取缓冲器中，并将相应的数据行发送到高速缓冲存储器。

3. 发明授权

US07277826B2 Apparatus and method for detecting and forecasting resource bottlenecks 有权
标题翻译：检测和预测资源瓶颈的装置和方法
公开(公告)号：US07277826B2
公开(公告)日：2007-10-02
申请号：US10647800
申请日：2003-08-25
申请人： Vittorio Castelli , Peter Franaszek , Luis A. Lastras
发明人： Vittorio Castelli , Peter Franaszek , Luis A. Lastras
IPC分类号： G06F11/30 , G21C17/00
CPC分类号： G06F11/3409 , G06F11/3452 , G06F2201/81
摘要： A system and method of detecting and forecasting resource bottlenecks of a computer system. In one aspect, a method includes the steps of: monitoring with successive measurements a utilization parameter of a system resource; computing a change parameter by comparing the differences between successive measurements of the utilization parameter; comparing the change parameter to a threshold change parameter; and reporting a resource bottleneck if the change parameter exceeds the threshold change parameter.
摘要翻译：一种检测和预测计算机系统资源瓶颈的系统和方法。一方面，一种方法包括以下步骤：通过连续测量监视系统资源的利用参数; 通过比较使用参数的连续测量之间的差异来计算变化参数; 将变化参数与阈值变化参数进行比较; 并且如果改变参数超过阈值变化参数则报告资源瓶颈。

4. 发明申请

US20060010295A1 Distributed storage for disk caching 审中-公开
标题翻译：用于磁盘缓存的分布式存储
公开(公告)号：US20060010295A1
公开(公告)日：2006-01-12
申请号：US10887420
申请日：2004-07-08
申请人： Peter Franaszek , Dan Poff
发明人： Peter Franaszek , Dan Poff
IPC分类号： G06F12/00
CPC分类号： G06F12/0866 , G06F3/061 , G06F3/0659 , G06F3/0664 , G06F3/067
摘要： We separate the control functions of the I/O from the actual caching and transfer of data. This is referred herein as “disk improvements.” For caching, this enables improved utilization of bandwidth and memory. For transfers of data, bandwidth is improved while retaining security. Also in the present invention, we utilize unused portions of host systems to serve as a cache. This is referred herein as “cache enhancements.”
摘要翻译：我们将I / O的控制功能与数据的实际缓存和传输分开。这在这里被称为“磁盘改进”。对于缓存，这样可以提高带宽和内存的利用率。为了传输数据，改善带宽并保持安全性。同样在本发明中，我们利用主机系统的未使用部分作为高速缓存。这在本文中被称为“缓存增强”。

5. 发明申请

US20070234323A1 Learning and cache management in software defined contexts 有权
标题翻译：在软件定义的上下文中学习和缓存管理
公开(公告)号：US20070234323A1
公开(公告)日：2007-10-04
申请号：US11355357
申请日：2006-02-16
申请人： Peter Franaszek , Luis Alfonso Montano , R. Tremaine
发明人： Peter Franaszek , Luis Alfonso Montano , R. Tremaine
IPC分类号： G06F9/45
CPC分类号： G06F8/4442 , G06F12/0862 , G06F2212/1021 , G06F2212/6028
摘要： A exemplary system and method are provided for learning and cache management in software defined contexts. Exemplary embodiments of the present invention described herein address the problem of the data access wall resulting from processor stalls due to the increasing discrepancies between processor speed and the latency of access to data that is not stored in the immediate vicinity of the processor requesting the data.
摘要翻译：提供了用于在软件定义的上下文中学习和缓存管理的示例性系统和方法。本文描述的本发明的示例性实施例解决了由于处理器速度与未存储在请求数据的处理器紧邻附近的数据的访问等待时间之间的差异而导致的处理器停顿所导致的数据访问壁的问题。

6. 发明申请

US20050235116A1 SYSTEM, METHOD AND STORAGE MEDIUM FOR PREFETCHING VIA MEMORY BLOCK TAGS 有权
标题翻译：用于通过存储块标签进行预制的系统，方法和存储介质
公开(公告)号：US20050235116A1
公开(公告)日：2005-10-20
申请号：US10709127
申请日：2004-04-15
申请人： Peter Franaszek , Luis Lastras
发明人： Peter Franaszek , Luis Lastras
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0862
摘要： A system for memory management including a tag cache in communication with one or more cache devices in a storage hierarchy. The tag cache includes tags of recently accessed memory blocks where each tag corresponds to one of the pages and each tag includes tag contents. The tag contents control which memory lines of the corresponding memory block are prefetched into at least one of the cache devices. The tag contents are updated using a selected subset of processor references. The subset is referred to as filtered references. The tag contents are modified probabilistically at selected time or events.
摘要翻译：一种用于存储器管理的系统，包括与存储层级中的一个或多个高速缓存设备通信的标签缓存。标签缓存包括最近访问的存储器块的标签，其中每个标签对应于其中一个页面，并且每个标签包括标签内容。标签内容控制对应的存储器块的哪些存储器行被预取到至少一个高速缓存器件中。使用选定的处理器引用子集来更新标签内容。该子集称为过滤引用。标签内容在选定的时间或事件中被概率地修改。

7. 发明授权

US07982636B2 Data compression using a nested hierachy of fixed phrase length static and dynamic dictionaries 有权
标题翻译：使用固定短语长度静态和动态词典的嵌套层次结构进行数据压缩
公开(公告)号：US07982636B2
公开(公告)日：2011-07-19
申请号：US12544726
申请日：2009-08-20
申请人： Bulent Abali , Mohammad Banikazemi , Peter Franaszek , Luis A. Lastras , Dan E. Poff
发明人： Bulent Abali , Mohammad Banikazemi , Peter Franaszek , Luis A. Lastras , Dan E. Poff
IPC分类号： H03M7/30
CPC分类号： H03M7/3088
摘要： The present invention describes lossless data compression/decompression methods and systems. A random access memory (RAM) operates as a static dictionary and includes commonly used strings/symbols/phrases/words. An input buffer operates as a dynamic dictionary and includes input strings/phrases/symbols/words. A set-associative cache memory operates as a hash table, and includes pointers pointing to the commonly used strings/symbols/phrases/words in the static dictionary and/or pointing to one or more of the input strings/phrases/symbols/words in the dynamic dictionary. Alternatively, the set-associative cache memory combines the dynamic dictionary, the static dictionary and the hash table. When encountering a symbol/phrase/string/word in the static or dynamic dictionary in an input stream, a compressor logic or module places a pointer pointing to the symbol/phrase/string/word at a current location on the output stream. The hash table may include phrases/symbols/strings/words and/or pointers pointing to phrases/symbols/strings/words.
摘要翻译：本发明描述了无损数据压缩/解压缩方法和系统。随机访问存储器（RAM）作为静态字典操作，并且包括常用的字符串/符号/短语/单词。输入缓冲器作为动态字典操作，包括输入字符串/短语/符号/字。集合关联高速缓冲存储器作为散列表操作，并且包括指向静态字典中常用的字符串/符号/短语/单词的指针和/或指向一个或多个输入字符串/短语/符号/单词中的一个或多个动态词典。或者，集合关联高速缓存存储器组合动态字典，静态字典和散列表。当在输入流中的静态或动态字典中遇到符号/短语/字符串/单词时，压缩器逻辑或模块将指向指向输出流上当前位置的符号/短语/字符串/字的指针放置。哈希表可以包括短语/符号/字符串/单词和/或指向短语/符号/字符串/单词的指针。

8. 发明申请

US20070294483A1 PAGE DESCRIPTORS FOR PREFETCHING AND MEMORY MANAGEMENT 有权
标题翻译：用于预制和存储管理的页面描述符
公开(公告)号：US20070294483A1
公开(公告)日：2007-12-20
申请号：US11844086
申请日：2007-08-23
申请人： Peter Franaszek
发明人： Peter Franaszek
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F2212/6022 , G06F2212/6024
摘要： A computer system and a method for enhancing the cache prefetch behavior. A computer system including a processor, a main memory, a prefetch controller, a cache memory, a prefetch buffer, and a main memory, wherein each page in the main memory has associated with it a tag, which is used for controlling the prefetching of a variable subset of lines from this page as well as lines from at least one other page. And, coupled to the processor is a prefetch controller, wherein the prefetch controller responds to the processor determining a fault (or miss) occurred to a line of data by fetching a corresponding line of data with the corresponding tag, with the corresponding tag to be stored in the prefetch buffer, and sending the corresponding line of data to the cache memory.
摘要翻译：一种用于增强缓存预取行为的计算机系统和方法。一种包括处理器，主存储器，预取控制器，高速缓冲存储器，预取缓冲器和主存储器的计算机系统，其中，主存储器中的每个页面与其相关联，该标签用于控制预取来自该页面的行的可变子集以及至少一个其他页面的行。并且，耦合到处理器的是预取控制器，其中预取控制器响应于处理器确定一行数据发生的故障（或未命中），通过相应的标签获取相应的数据行，相应的标签为存储在预取缓冲器中，并将相应的数据行发送到高速缓冲存储器。

9. 发明申请

US20070204109A1 SYSTEM, METHOD AND STORAGE MEDIUM FOR PREFETCHING VIA MEMORY BLOCK TAGS 有权
标题翻译：用于通过存储块标签进行预制的系统，方法和存储介质
公开(公告)号：US20070204109A1
公开(公告)日：2007-08-30
申请号：US11743697
申请日：2007-05-03
申请人： Peter Franaszek , Luis Lastras
发明人： Peter Franaszek , Luis Lastras
IPC分类号： G06F12/00
CPC分类号： G06F12/0862
摘要： A method and system for memory management are provided. The system includes a tag cache in communication with one or more cache devices in a storage hierarchy. The tag cache includes tags of recently accessed memory blocks, each tag corresponding to one of the memory blocks and including tag contents. The tag contents control which memory lines of the corresponding memory block are prefetched into at least one of the cache devices. The tag contents further include a bit to control prefetching of memory lines from a next virtual memory block, the bit referred to as a next virtual memory block bit. The next virtual memory block bit in a preceding memory block in a virtual address space is set to a prefetch status when the preceding memory block tag is in the tag cache.
摘要翻译：提供了一种用于存储器管理的方法和系统。该系统包括与存储层级中的一个或多个缓存设备通信的标签缓存。标签缓存包括最近访问的存储器块的标签，每个标签对应于一个存储器块并且包括标签内容。标签内容控制对应的存储器块的哪些存储器行被预取到至少一个高速缓存器件中。标签内容还包括用于控制来自下一个虚拟存储器块的存储器行预取的位，该位被称为下一个虚拟存储器块位。虚拟地址空间中前一个存储块中的下一个虚拟内存块位被设置为当前一个存储块标记位于标记高速缓存中时的预取状态。

10. 发明授权

US07103722B2 Cache configuration for compressed memory systems 失效
标题翻译：压缩内存系统的缓存配置
公开(公告)号：US07103722B2
公开(公告)日：2006-09-05
申请号：US10200937
申请日：2002-07-22
申请人： Caroline Benveniste , Peter Franaszek , John T. Robinson , Charles Schulz
发明人： Caroline Benveniste , Peter Franaszek , John T. Robinson , Charles Schulz
IPC分类号： G06F12/00
CPC分类号： G06F12/127 , G06F12/0813 , G06F12/0864 , G06F2212/2542 , G06F2212/401
摘要： A method and structure is disclosed for constraining cache line replacement that processes a cache miss in a computer system. The invention contains a K-way set associative cache that selects lines in the cache for replacement. The invention constrains the selecting process so that only a predetermined subset of each set of cache lines is selected for replacement. The subset has at least a single cache line and the set size is at least two cache lines. The invention may further select between at least two cache lines based upon which of the cache lines was accessed least recently. A selective enablement of the constraining process is based on a free space memory condition of a memory associated with the cache memory. The invention may further constrain cache line replacement based upon whether the cache miss is from a non-local node in a nonuniform-memory-access system. The invention may also process cache writes so that a predetermined subset of each set is known to be in an unmodified state.
摘要翻译：公开了一种用于约束处理计算机系统中的高速缓存未命中的高速缓存行替换的方法和结构。本发明包含一个K路组合关联高速缓存，用于选择高速缓存中的行进行替换。本发明限制了选择过程，使得仅选择每组高速缓存行的预定子集用于替换。该子集具有至少一条缓存行，并且集合大小至少为两条缓存行。本发明还可以基于最近访问哪个高速缓存行，在至少两条高速缓存行之间进行选择。约束过程的选择性启用基于与高速缓存存储器相关联的存储器的空闲存储器条件。本发明还可以基于高速缓存未命中来自非均匀存储器访问系统中的非本地节点来进一步约束高速缓存行替换。本发明还可以处理高速缓存写入，使得每组的预定子集已知处于未修改状态。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式