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1. 发明授权

US08609308B1 Smart subfield method for E-beam lithography 有权
公开(公告)号：US08609308B1
公开(公告)日：2013-12-17
申请号：US13484434
申请日：2012-05-31
申请人： Pei-Shiang Chen , Hung-Chun Wang , Jeng-Horng Chen , Cheng-Hung Chen , Shih-Chi Wang , Nian-Fuh Cheng , Chia-Chi Lin
发明人： Pei-Shiang Chen , Hung-Chun Wang , Jeng-Horng Chen , Cheng-Hung Chen , Shih-Chi Wang , Nian-Fuh Cheng , Chia-Chi Lin
IPC分类号： G03F9/00 , G03C5/00
CPC分类号： G06F17/5068 , G03F7/20 , H01J37/3174 , H01J2237/31764 , H01J2237/31769 , Y10S430/143
摘要： The present disclosure provides a method of improving a layer to layer overlay error by an electron beam lithography system. The method includes generating a smart boundary of two subfields at the first pattern layer and obeying the smart boundary at all consecutive pattern layers. The same subfield is exposed by the same electron beam writer at all pattern layers. The overlay error caused by the different electron beam at different layer is improved.

2. 发明申请

US20130323648A1 SMART SUBFIELD METHOD FOR E-BEAM LITHOGRAPHY 有权
标题翻译：用于电子束光刻的SMART SUBFIELD方法
公开(公告)号：US20130323648A1
公开(公告)日：2013-12-05
申请号：US13484434
申请日：2012-05-31
申请人： Pei-Shiang Chen , Hung-Chun Wang , Jeng-Horng Chen , Cheng-Hung Chen , Shih-Chi Wang , Nian-Fuh Cheng , Chia-Chi Lin
发明人： Pei-Shiang Chen , Hung-Chun Wang , Jeng-Horng Chen , Cheng-Hung Chen , Shih-Chi Wang , Nian-Fuh Cheng , Chia-Chi Lin
IPC分类号： G03F7/20
CPC分类号： G06F17/5068 , G03F7/20 , H01J37/3174 , H01J2237/31764 , H01J2237/31769 , Y10S430/143
摘要： The present disclosure provides a method of improving a layer to layer overlay error by an electron beam lithography system. The method includes generating a smart boundary of two subfields at the first pattern layer and obeying the smart boundary at all consecutive pattern layers. The same subfield is exposed by the same electron beam writer at all pattern layers. The overlay error caused by the different electron beam at different layer is improved.
摘要翻译：本公开提供了一种通过电子束光刻系统改善层间覆盖误差的方法。该方法包括在第一图案层处生成两个子场的智能边界，并在所有连续图案层处遵循智能边界。相同的子场在相同的电子束写入器在所有图案层曝光。改善了不同电子束在不同层面引起的覆盖误差。

3. 发明申请

US20130055173A1 GEOMETRIC PATTERN DATA QUALITY VERIFICATION FOR MASKLESS LITHOGRAPHY 有权
标题翻译：几何图形数据质量验证用于MASKLESS LITHOGRAPHY
公开(公告)号：US20130055173A1
公开(公告)日：2013-02-28
申请号：US13217345
申请日：2011-08-25
申请人： Hung-Chun Wang , Pei-Shiang Chen , Tzu-Chin Lin , Cheng-Hung Chen , Shih-Chi Wang , Nian-Fuh Cheng , Jeng-Horng Chen , Wen-Chun Huang , Ru-Gun Liu
发明人： Hung-Chun Wang , Pei-Shiang Chen , Tzu-Chin Lin , Cheng-Hung Chen , Shih-Chi Wang , Nian-Fuh Cheng , Jeng-Horng Chen , Wen-Chun Huang , Ru-Gun Liu
IPC分类号： G06F17/50
CPC分类号： G03F7/2059
摘要： The present disclosure involves a method of performing a maskless lithography process. The method includes providing a proximity correction pattern. The method includes generating a deformed pattern based on the proximity correction pattern. The method includes performing a first convolution process to the proximity correction pattern to generate a first proximity correction pattern contour. The method includes processing the first proximity correction pattern contour to generate a second proximity correction pattern contour. The method includes performing a second convolution process to the deformed pattern to generate a first deformed pattern contour. The method includes processing the first deformed pattern contour to generate a second deformed pattern contour. The method includes identifying mismatches between the second proximity correction pattern contour and the second deformed pattern contour. The method includes determining whether the deformed pattern is lithography-ready in response to the identifying.
摘要翻译：本公开涉及执行无掩模光刻工艺的方法。该方法包括提供接近校正模式。该方法包括基于接近校正图案生成变形图案。该方法包括对接近校正图案执行第一卷积处理以产生第一邻近校正图案轮廓。该方法包括处理第一接近校正图案轮廓以产生第二邻近校正图案轮廓。该方法包括对变形图案执行第二卷积处理以产生第一变形图案轮廓。该方法包括处理第一变形图案轮廓以产生第二变形图案轮廓。该方法包括识别第二接近校正图案轮廓和第二变形图案轮廓之间的不匹配。该方法包括响应于识别确定变形图案是否是光刻刻画的。

4. 发明授权

US08601407B2 Geometric pattern data quality verification for maskless lithography 有权
标题翻译：无掩模光刻的几何图形数据质量验证
公开(公告)号：US08601407B2
公开(公告)日：2013-12-03
申请号：US13217345
申请日：2011-08-25
申请人： Hung-Chun Wang , Pei-Shiang Chen , Tzu-Chin Lin , Cheng-Hung Chen , Shih-Chi Wang , Nian-Fuh Cheng , Jeng-Horng Chen , Wen-Chun Huang , Ru-Gun Liu
发明人： Hung-Chun Wang , Pei-Shiang Chen , Tzu-Chin Lin , Cheng-Hung Chen , Shih-Chi Wang , Nian-Fuh Cheng , Jeng-Horng Chen , Wen-Chun Huang , Ru-Gun Liu
IPC分类号： G06F17/50
CPC分类号： G03F7/2059
摘要： Provided is a method of performing a maskless lithography process. The method includes providing a proximity correction pattern. The method includes generating a deformed pattern based on the proximity correction pattern. The method includes performing a first convolution process to the proximity correction pattern to generate a first proximity correction pattern contour. The method includes processing the first proximity correction pattern contour to generate a second proximity correction pattern contour. The method includes performing a second convolution process to the deformed pattern to generate a first deformed pattern contour. The method includes processing the first deformed pattern contour to generate a second deformed pattern contour. The method includes identifying mismatches between the second proximity correction pattern contour and the second deformed pattern contour. The method includes determining whether the deformed pattern is lithography-ready in response to the identifying.
摘要翻译：提供了进行无掩模光刻处理的方法。该方法包括提供接近校正模式。该方法包括基于接近校正图案生成变形图案。该方法包括对接近校正图案执行第一卷积处理以产生第一邻近校正图案轮廓。该方法包括处理第一接近校正图案轮廓以产生第二邻近校正图案轮廓。该方法包括对变形图案执行第二卷积处理以产生第一变形图案轮廓。该方法包括处理第一变形图案轮廓以产生第二变形图案轮廓。该方法包括识别第二接近校正图案轮廓和第二变形图案轮廓之间的不匹配。该方法包括响应于识别确定变形图案是否是光刻刻画的。

5. 发明授权

US08563224B1 Data process for E-beam lithography 有权
标题翻译：电子束光刻数据处理
公开(公告)号：US08563224B1
公开(公告)日：2013-10-22
申请号：US13487850
申请日：2012-06-04
申请人： Cheng-Hung Chen , Pei-Shiang Chen , Shih-Chi Wang , Jeng-Horng Chen
发明人： Cheng-Hung Chen , Pei-Shiang Chen , Shih-Chi Wang , Jeng-Horng Chen
IPC分类号： G03C5/00 , G03F1/20
CPC分类号： G06F17/50 , G03C5/00 , G03F1/20 , H01J2237/31762 , H01J2237/31764 , H01J2237/31769 , Y10S430/143
摘要： The present disclosure provides a dithering method of increasing wafer throughput by an electron beam lithography system. The dithering method generates an edge map from a vertex map. The vertex map is generated from an integrated circuit design layout (such as an original pattern bitmap). A gray map (also referred to as a pattern gray map) is also generated from the integrated circuit design layout. By combining the edge map with the gray map, a modified integrated circuit design layout (modified pattern bitmap) is generated for use by the electron beam lithography system.
摘要翻译：本公开提供了通过电子束光刻系统增加晶片生产量的抖动方法。抖动方法从顶点图生成边缘图。顶点图是从集成电路设计布局（如原始图案位图）生成的。也从集成电路设计布局生成灰色地图（也称为图案灰度图）。通过将边缘图与灰度图组合，生成修改后的集成电路设计布局（修改图案位图），供电子束光刻系统使用。

6. 发明申请

US20130320243A1 EFFICIENT SCAN FOR E-BEAM LITHOGRAPHY 有权
标题翻译： E-BEAM LITHOGRAPHY的高效扫描
公开(公告)号：US20130320243A1
公开(公告)日：2013-12-05
申请号：US13484524
申请日：2012-05-31
申请人： Cheng-Hung Chen , Shih-Chi Wang , Jeng-Horng Chen , Burn Jeng Lin
发明人： Cheng-Hung Chen , Shih-Chi Wang , Jeng-Horng Chen , Burn Jeng Lin
IPC分类号： G21K5/10
CPC分类号： H01J37/3174 , B82Y10/00 , B82Y40/00 , H01J2237/31761
摘要： The present disclosure provides a method of increasing the wafer throughput by an electron beam lithography system. The method includes scanning a wafer using the maximum scan slit width (MSSW) of the electron beam writer. By constraining the integrated circuit (IC) field size to allow the MSSW to cover a complete field, the MSSW is applied to decrease the scan lanes of a wafer and thereby increase the throughput. When scanning the wafer with the MSSW, the next scan lane data can be rearranged and loaded into a memory buffer. Thus, once one scan lane is finished, the next scan lane data in the memory buffer is read for scanning.
摘要翻译：本公开提供了一种通过电子束光刻系统增加晶片通过量的方法。该方法包括使用电子束写入器的最大扫描狭缝宽度（MSSW）扫描晶片。通过限制集成电路（IC）场尺寸以允许MSSW覆盖整个场，MSSW被应用于减小晶片的扫描通道，从而增加吞吐量。当用MSSW扫描晶片时，下一个扫描通道数据可以重新排列并加载到存储器缓冲器中。因此，一旦一个扫描通道完成，读取存储器缓冲器中的下一个扫描通道数据进行扫描。

7. 发明授权

US08987689B2 Efficient scan for E-beam lithography 有权
标题翻译：电子束光刻的高效扫描
公开(公告)号：US08987689B2
公开(公告)日：2015-03-24
申请号：US13484524
申请日：2012-05-31
申请人： Cheng-Hung Chen , Shih-Chi Wang , Jeng-Horng Chen , Burn Jeng Lin
发明人： Cheng-Hung Chen , Shih-Chi Wang , Jeng-Horng Chen , Burn Jeng Lin
IPC分类号： A61N5/00
CPC分类号： H01J37/3174 , B82Y10/00 , B82Y40/00 , H01J2237/31761
摘要： The present disclosure provides a method of increasing the wafer throughput by an electron beam lithography system. The method includes scanning a wafer using the maximum scan slit width (MSSW) of the electron beam writer. By constraining the integrated circuit (IC) field size to allow the MSSW to cover a complete field, the MSSW is applied to decrease the scan lanes of a wafer and thereby increase the throughput. When scanning the wafer with the MSSW, the next scan lane data can be rearranged and loaded into a memory buffer. Thus, once one scan lane is finished, the next scan lane data in the memory buffer is read for scanning.
摘要翻译：本公开提供了一种通过电子束光刻系统增加晶片通过量的方法。该方法包括使用电子束写入器的最大扫描狭缝宽度（MSSW）扫描晶片。通过限制集成电路（IC）场尺寸以允许MSSW覆盖整个场，MSSW被应用于减小晶片的扫描通道，从而增加吞吐量。当用MSSW扫描晶片时，可以将下一个扫描通道数据重新排列并加载到存储器缓冲器中。因此，一旦一个扫描通道完成，读取存储器缓冲器中的下一个扫描通道数据进行扫描。

8. 发明申请

US20140098327A1 STRUCTURE OF POLARIZER AND LIQUID CRYSTAL PANEL 审中-公开
标题翻译：极化和液晶板的结构
公开(公告)号：US20140098327A1
公开(公告)日：2014-04-10
申请号：US13699695
申请日：2012-10-12
申请人： Cheng-Hung Chen
发明人： Cheng-Hung Chen
IPC分类号： G02B5/30 , G02F1/1335
CPC分类号： G02B5/30 , G02B5/3025 , G02F1/133528
摘要： The present invention provides a structure of polarizer and liquid crystal panel. The polarizer includes, from top down, polarizer main body, electrostatic adsorption film and release film. The LC panel includes a polarizer of the structure. Because the polarizer replaces the PSA of the known polarizer with the electrostatic adsorption film, the electrostatic adsorption film uses electrostatic adsorption to attach the polarizer main body to the substrate of the LC panel without using any adhesive. Therefore, when reprocessing is required, no residual adhesive on substrate is left to removal and the cleaning is convenient. Also, electrostatic adsorption film will not damage the polarizer when removed from the substrate so that the polarizer can be reused to effectively save the cost.
摘要翻译：本发明提供了偏振器和液晶面板的结构。起偏器包括从上到下的偏振器主体，静电吸附膜和脱模膜。 LC面板包括该结构的偏振器。由于偏振器用静电吸附膜代替已知偏振片的PSA，所以静电吸附膜使用静电吸附将偏振器主体附着在LC面板的基板上，而不使用任何粘合剂。因此，当需要再加工时，基板上没有残留的粘合剂被去除并且清洁是方便的。此外，当从基板去除时，静电吸附膜不会损坏偏振器，使得可以重新使用偏振器以有效地节省成本。

9. 发明申请

US20130093990A1 LIQUID CRYSTAL DISPLAY MODULE AND A LIQUID CRYSTAL DISPLAY PANEL 审中-公开
标题翻译：液晶显示模块和液晶显示面板
公开(公告)号：US20130093990A1
公开(公告)日：2013-04-18
申请号：US13376605
申请日：2011-10-27
申请人： Shyhfeng Chen , Cheng-Hung Chen , Jinjie Wang
发明人： Shyhfeng Chen , Cheng-Hung Chen , Jinjie Wang
IPC分类号： G02F1/1345
CPC分类号： G02F1/13458 , H05K1/117 , H05K1/118 , H05K3/361 , H05K3/363 , H05K2201/09709 , H05K2201/09918
摘要： A liquid crystal display module is provided, which includes a display panel. The display panel disposes a plurality of panel solder pads. Two ends of each panel solder pad both dispose a wire longitudinally extending. The length of each panel solder pad longitudinally extends along a wire direction. The module further includes a FPC board, which has a plurality of FPC board solder pads. The FPC board solder pads and the panel solder pads are soldered together in a one-to-one corresponding relational manner after being aligned with each other by a machine. Two adjacent panel solder pads are stagger arranged along the wire direction. A distance between one panel solder pad and the corresponding wire of the other panel solder pad along the direction perpendicular to the wire is greater than a minimum of an alignment precision of the machine. A liquid crystal display panel is also provided.
摘要翻译：提供一种包括显示面板的液晶显示模块。显示面板配置多个面板焊盘。每个面板焊盘的两端均布置纵向延伸的导线。每个面板焊盘的长度沿线方向纵向延伸。该模块还包括FPC板，其具有多个FPC板焊盘。 FPC板焊盘和面板焊盘在通过机器彼此对准之后以一对一的对应关系方式被焊接在一起。两个相邻的面板焊盘沿着线方向错开。一个面板焊盘和另一个面板焊盘的相对应的线沿垂直于导线的方向的距离大于机器的对准精度的最小值。还提供了一种液晶显示面板。

10. 发明授权

US08638412B2 Thin film transistor liquid crystal display device, substrate, and manufacturing method thereof 有权
标题翻译：薄膜晶体管液晶显示装置，基板及其制造方法
公开(公告)号：US08638412B2
公开(公告)日：2014-01-28
申请号：US13503656
申请日：2012-02-23
申请人： Cheng-Hung Chen
发明人： Cheng-Hung Chen
IPC分类号： G02F1/1343
CPC分类号： G02F1/1362 , G02F2001/134345 , G02F2201/123
摘要： The present invention discloses a thin-film transistor (TFT) liquid crystal display device, a substrate, and a manufacturing method thereof. The TFT substrate includes: a glass substrate and signal lines, scan lines, a first pixel electrode, a second pixel electrode, a common electrode, and the TFT. The first pixel electrode and the second pixel electrode at least partially overlap each other. The second pixel electrode forms a plurality of horizontally arranged slits and the first pixel electrode forms a hollow structure in a portion overlapping the second pixel electrode. Through the above method, the present invention increases transmittance, improve view angle color shift, and improve the quality of image.
摘要翻译：本发明公开了一种薄膜晶体管（TFT）液晶显示装置，基板及其制造方法。 TFT基板包括：玻璃基板和信号线，扫描线，第一像素电极，第二像素电极，公共电极和TFT。第一像素电极和第二像素电极至少部分地彼此重叠。第二像素电极形成多个水平布置的狭缝，并且第一像素电极在与第二像素电极重叠的部分中形成中空结构。通过上述方法，本发明提高透光率，提高视角色偏，提高图像质量。

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