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1. 发明授权

US07281074B2 Method and apparatus to quiesce USB activities using interrupt descriptor caching and asynchronous notifications 有权
公开(公告)号：US07281074B2
公开(公告)日：2007-10-09
申请号：US11171833
申请日：2005-06-29
申请人： Paul S. Diefenbaugh , James Kardach , Barnes Cooper , Leslie E. Cline
发明人： Paul S. Diefenbaugh , James Kardach , Barnes Cooper , Leslie E. Cline
IPC分类号： G06F13/10 , G06F13/38 , G06F13/14
CPC分类号： G06F13/24 , G06F13/12
摘要： In one embodiment, a data processing system includes, but is not limited to, a processor, a memory coupled to the processor, and a universal serial bus (USB) controller coupled to the processor and the memory. The USB controller includes a local memory to cache at least one activity descriptor of at least a portion of a periodic schedule having multiple frames stored in the main memory. The USB controller defers to service an active USB device described by one of the activity descriptors until a corresponding frame is scheduled to be serviced subsequently. Other methods and apparatuses are also described.

2. 发明申请

US20150169036A1 RESCHEDULING WORKLOADS TO ENFORCE AND MAINTAIN A DUTY CYCLE 有权
标题翻译：减少执行和维护一个占空比的工作量
公开(公告)号：US20150169036A1
公开(公告)日：2015-06-18
申请号：US14109388
申请日：2013-12-17
申请人： Inder M. Sodhi , Barnes Cooper , Paul S. Diefenbaugh , Faraz A. Siddiqi , Michael Calyer , Andrew D. Henroid , Ruchika Singh
发明人： Inder M. Sodhi , Barnes Cooper , Paul S. Diefenbaugh , Faraz A. Siddiqi , Michael Calyer , Andrew D. Henroid , Ruchika Singh
IPC分类号： G06F1/32 , G06F9/48
CPC分类号： G06F1/3243 , G06F1/3287 , G06F1/329 , G06F9/4893 , Y02D10/171 , Y02D10/24 , Y02D50/20
摘要： In an embodiment, a processor includes a plurality of cores to independently execute instructions, at least one graphics engine to independently execute graphics instructions, and a power controller including an alignment logic to cause at least one workload to be executed on a first core to be rescheduled to a different time to enable the plurality of cores to be active during an active time window and to be in a low power state during an idle time window. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括多个核以独立地执行指令，至少一个图形引擎来独立地执行图形指令;以及功率控制器，其包括对准逻辑，以使至少一个工作负载在第一个核上被执行为重新安排到不同的时间，以使得多个核心在活动时间窗口期间是活动的，并且在空闲时间窗口期间处于低功率状态。描述和要求保护其他实施例。

3. 发明授权

US08631257B2 Platform power management based on latency guidance 有权
标题翻译：基于延迟指导的平台电源管理
公开(公告)号：US08631257B2
公开(公告)日：2014-01-14
申请号：US13445809
申请日：2012-04-12
申请人： Jaya L. Jeyaseelan , Neil Songer , Barnes Cooper , Paul S. Diefenbaugh
发明人： Jaya L. Jeyaseelan , Neil Songer , Barnes Cooper , Paul S. Diefenbaugh
IPC分类号： G06F1/16
CPC分类号： G06F1/3203
摘要： Embodiments of a system for receiving power management guidelines from a first plurality of components of a system, and developing a power management policy to manage one or more of a second plurality of components of the system based at least in part on the received power management guidelines. Other embodiments are described.
摘要翻译：用于从系统的第一多个组件接收功率管理指南的系统的实施例，以及至少部分地基于所接收的功率管理指南来开发用于管理系统的第二多个组件中的一个或多个的功率管理策略。描述其他实施例。

4. 发明申请

US20120198248A1 PLATFORM POWER MANAGEMENT BASED ON LATENCY GUIDANCE 有权
标题翻译：基于LATENCY指导的平台电源管理
公开(公告)号：US20120198248A1
公开(公告)日：2012-08-02
申请号：US13445809
申请日：2012-04-12
申请人： Jaya L. Jeyaseelan , Neil Songer , Barnes Cooper , Paul S. Diefenbaugh
发明人： Jaya L. Jeyaseelan , Neil Songer , Barnes Cooper , Paul S. Diefenbaugh
IPC分类号： G06F1/00
CPC分类号： G06F1/3203
摘要： Embodiments of a system for receiving power management guidelines from a first plurality of components of a system, and developing a power management policy to manage one or more of a second plurality of components of the system based at least in part on the received power management guidelines. Other embodiments are described.
摘要翻译：用于从系统的第一多个组件接收功率管理指南的系统的实施例，以及至少部分地基于所接收的功率管理指南来开发用于管理系统的第二多个组件中的一个或多个的功率管理策略。描述其他实施例。

5. 发明申请

US20150355705A1 Forcing A Processor Into A Low Power State 有权
标题翻译：将处理器强制为低功耗状态
公开(公告)号：US20150355705A1
公开(公告)日：2015-12-10
申请号：US14298171
申请日：2014-06-06
申请人： Eliezer Weissmann , Yoni Aizik , Doron Rajwan , Nir Rosenzweig , Efraim Rotem , Barnes Cooper , Paul S. Diefenbaugh , Guy M. Therien , Michael Mishaeli , Nadav Shulman , Ido Melamed , Niv Tokman , Alexander Gendler , Arik Gihon , Yevgeni Sabin , Hisham Abu Salah , Esfir Natanzon
发明人： Eliezer Weissmann , Yoni Aizik , Doron Rajwan , Nir Rosenzweig , Efraim Rotem , Barnes Cooper , Paul S. Diefenbaugh , Guy M. Therien , Michael Mishaeli , Nadav Shulman , Ido Melamed , Niv Tokman , Alexander Gendler , Arik Gihon , Yevgeni Sabin , Hisham Abu Salah , Esfir Natanzon
IPC分类号： G06F1/32
CPC分类号： G06F1/3287 , G06F1/3203 , G06F1/324 , G06F11/0757 , Y02D10/126 , Y02D10/171 , Y02D50/20
摘要： In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括多个核心和功率控制器。功率控制器可以包括硬件占空比（HDC）逻辑，以便即使逻辑处理器具有要执行的工作负载来使得一个核的至少一个逻辑处理器进入强制空闲状态。此外，如果至少另外一个其他逻辑处理器被阻止进入强制空闲状态，则HDC逻辑可以导致逻辑处理器在空闲周期结束之前退出强制空闲状态。描述和要求保护其他实施例。

6. 发明授权

US07027057B2 Entering and exiting power managed states without disrupting accelerated graphics port transactions 失效
公开(公告)号：US07027057B2
公开(公告)日：2006-04-11
申请号：US10640196
申请日：2003-08-12
申请人： Satchit Jain , Debra T. Cohen , Leslie E. Cline , Barnes Cooper , Anil V. Nanduri
发明人： Satchit Jain , Debra T. Cohen , Leslie E. Cline , Barnes Cooper , Anil V. Nanduri
IPC分类号： G06F13/14 , G06F1/26 , G06F1/32 , G06F13/28 , G09F5/39
CPC分类号： G06T17/00 , G06F1/3203
摘要： An interface between an accelerated graphics port graphics controller (AGP-GC) and a core controller to prevent entry into a low power state from interfering with transfers to or from the AGP-GC that have been requested but not completed. The core controller can communicate to the AGP-GC an intent to enter a low power state, while the AGP-GC can communicate to the core controller the busy status of the AGP-GC. When the AGP-GC receives notice of an intent to enter a low power state, it can stop issuing requests to the core controller. When the core controller detects that the AGP-GC is busy, the core controller can postpone entry into the low power state until the AGP-GC completes any requests that are in progress. In an alternate use of the interface, if the AGP-GC wishes to make a request during a low power state, it can signal the core controller of this need by indicating a busy status, which can trigger the core controller to initiate an exit from the low power state.

7. 发明授权

US06738068B2 Entering and exiting power managed states without disrupting accelerated graphics port transactions 有权
标题翻译：进入和退出电源管理状态，而不会中断加速图形端口事务
公开(公告)号：US06738068B2
公开(公告)日：2004-05-18
申请号：US09751441
申请日：2000-12-29
申请人： Debra T. Cohen , Leslie E. Cline , Barnes Cooper , Satchit Jain , Anil V. Nanduri
发明人： Debra T. Cohen , Leslie E. Cline , Barnes Cooper , Satchit Jain , Anil V. Nanduri
IPC分类号： G06F1314
CPC分类号： G06T17/00 , G06F1/3203
摘要： An interface between an accelerated graphics port graphics controller (AGP-GC) and a core controller to prevent entry into a low power state from interfering with transfers to or from the AGP-GC that have been requested but not completed. The core controller can communicate to the AGP-GC an intent to enter a low power state, while the AGP-GC can communicate to the core controller the busy status of the AGP-GC. When the AGP-GC receives notice of an intent to enter a low power state, it can stop issuing requests to the core controller. When the core controller detects that the AGP-GC is busy, the core controller can postpone entry into the low power state until the AGP-GC completes any requests that are in progress. In an alternate use of the interface, if the AGP-GC wishes to make a request during a low power state, it can signal the core controller of this need by indicating a busy status, which can trigger the core controller to initiate an exit from the low power state.
摘要翻译：加速图形端口图形控制器（AGP-GC）和核心控制器之间的接口，以防止进入低功率状态，干扰来自AGP-GC的请求但尚未完成的传输。核心控制器可以与AGP-GC进行通信，意图进入低功率状态，而AGP-GC可以与核心控制器通信AGP-GC的忙碌状态。当AGP-GC接收到进入低功率状态的意图时，可以停止向核心控制器发出请求。当核心控制器检测到AGP-GC正忙时，核心控制器可以推迟进入低功率状态，直到AGP-GC完成任何正在进行的请求。在接口的替代使用中，如果AGP-GC希望在低功率状态期间发出请求，则可以通过指示忙状态来向核心控制器通知该核心控制器，这可以触发核心控制器发起退出低功率状态。

8. 发明授权

US07472289B2 Audio noise mitigation for power state transitions 失效
标题翻译：功率状态转换的音频噪声抑制
公开(公告)号：US07472289B2
公开(公告)日：2008-12-30
申请号：US11019791
申请日：2004-12-21
申请人： Jorge P. Rodriguez , Leslie E. Cline , Barnes Cooper
发明人： Jorge P. Rodriguez , Leslie E. Cline , Barnes Cooper
IPC分类号： G06F1/00 , H04B15/00
CPC分类号： G06F1/3203
摘要： An audio noise mitigation approach. For one aspect, a first voltage associated with a first power management state is provided. A signal responsive to an indication associated with at least a first type of periodic exit event is received and responsive to the signal, a transition to a second voltage associated with a second state is initiated, a rate of the transition to the second voltage being slower than a similar voltage transition initiated in response to a non-periodic exit event.
摘要翻译：音频噪声缓解方法。一方面，提供与第一电源管理状态相关联的第一电压。接收响应于与至少第一类型的周期性退出事件相关联的指示的信号并且响应于该信号，开始向与第二状态相关联的第二电压的转变，到第二电压的转变的速率较慢而不是响应于非周期性退出事件而发起的类似电压转换。

9. 发明授权

US08176341B2 Platform power management based on latency guidance 有权
标题翻译：基于延迟指导的平台电源管理
公开(公告)号：US08176341B2
公开(公告)日：2012-05-08
申请号：US12059992
申请日：2008-03-31
申请人： Jaya L. Jeyaseelan , Neil Songer , Barnes Cooper , Paul S. Diefenbaugh
发明人： Jaya L. Jeyaseelan , Neil Songer , Barnes Cooper , Paul S. Diefenbaugh
IPC分类号： G06F27/28
CPC分类号： G06F1/3203
摘要： Embodiments of a system for receiving power management guidelines from a first plurality of components of a system, and developing a power management policy to manage one or more of a second plurality of components of the system based at least in part on the received power management guidelines. Other embodiments are described.
摘要翻译：用于从系统的第一多个组件接收功率管理指南的系统的实施例，以及至少部分地基于所接收的功率管理指南来开发用于管理系统的第二多个组件中的一个或多个的功率管理策略。描述其他实施例。

10. 发明申请

US20090249103A1 PLATFORM POWER MANAGEMENT BASED ON LATENCY GUIDANCE 有权
标题翻译：基于LATENCY指导的平台电源管理
公开(公告)号：US20090249103A1
公开(公告)日：2009-10-01
申请号：US12059992
申请日：2008-03-31
申请人： Jaya L. Jeyaseelan , Neil Songer , Barnes Cooper , Paul S. Diefenbaugh
发明人： Jaya L. Jeyaseelan , Neil Songer , Barnes Cooper , Paul S. Diefenbaugh
IPC分类号： G06F1/00
CPC分类号： G06F1/3203
摘要： Embodiments of a system for receiving power management guidelines from a first plurality of components of a system, and developing a power management policy to manage one or more of a second plurality of components of the system based at least in part on the received power management guidelines. Other embodiments are described.
摘要翻译：用于从系统的第一多个组件接收功率管理指南的系统的实施例，以及至少部分地基于所接收的功率管理指南来开发用于管理系统的第二多个组件中的一个或多个的功率管理策略。描述其他实施例。

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