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1. 发明授权

US07151473B2 Digital detection of blockers for wireless receiver 有权
标题翻译：无线接收机阻塞器的数字检测
公开(公告)号：US07151473B2
公开(公告)日：2006-12-19
申请号：US11203717
申请日：2005-08-15
申请人： Paul H. Fontaine , Ahmed Mohieldin , Pascal Audinot , Abdellatif Bellaouar , Mikael Guenais
发明人： Paul H. Fontaine , Ahmed Mohieldin , Pascal Audinot , Abdellatif Bellaouar , Mikael Guenais
IPC分类号： H03M1/84
CPC分类号： H03M3/36 , H03M3/486 , H03M3/49
摘要： A receiver 100 is provided. The receiver 100 comprises an in-phase analog-to-digital converter 112 operable to detect a saturation condition of the in-phase analog-to-digital converter 112 and to adjust the amplitude of a in-phase signal processed by the in-phase analog-to-digital converter 112 to remove the in-phase analog-to-digital converter 112 from the saturation condition and a in-phase digital filter 114 operable to adjust a gain applied to a digital input to the in-phase digital filter 114 from the in-phase analog-to-digital converter 112, the adjustment of the gain substantially inversely proportional to the adjustment of the amplitude of the in-phase signal processed by the in-phase analog-to-digital converter 112. In an embodiment, the receiver 100 also comprises a quadrature path that is substantially similar to the in-phase path, and the in-phase path and the quadrature path comprise a direct conversion receiver. In an embodiment, the in-phase analog-to-digital converter 112 and the in-phase digital filter 114 comprise an intermediate frequency receiver.
摘要翻译：提供接收器100。接收器100包括同相模拟数字转换器112，其可操作以检测同相模数转换器112的饱和状态，并调整由同相模数转换器112处理的同相信号的振幅模数转换器112以从饱和状态除去同相模数转换器112;以及同相数字滤波器114，其可操作以调整施加到同相数字滤波器114的数字输入的增益来自同相模数转换器112的增益基本上与由同相模数转换器112处理的同相信号的振幅的调整成反比。在一个实施例中，接收器100还包括基本上类似于同相路径的正交路径，并且同相路径和正交路径包括直接转换接收器。在一个实施例中，同相模数转换器112和同相数字滤波器114包括中频接收器。

2. 发明授权

US06806780B2 Efficient modulation compensation of sigma delta fractional phase locked loop 有权
$Efficient modulation compensation of sigma delta fractional phase locked loop$
标题翻译： Σ-Δ分数锁相环的高效调制补偿
公开(公告)号：US06806780B2
公开(公告)日：2004-10-19
申请号：US10387850
申请日：2003-03-13
申请人： Paul H. Fontaine , Abdellatif Bellaouar , Bertan Bakkaloglu
发明人： Paul H. Fontaine , Abdellatif Bellaouar , Bertan Bakkaloglu
IPC分类号： H03L700
CPC分类号： H03C3/0933 , H03C3/0925 , H03L7/1976
摘要： A technique is provided for achieving efficient modulation compensation of a &Sgr;&Dgr; fractional PLL. The parameters of the PLL TF are the gain, Kpll, of the PLL and the time constants associated with the loop filter. A careful design of the PLL allows setting the poles and zeros of the PLL TF to fixed values, independent of process and temperature. The unknown parameters of the system are then reduced to one: the PLL gain, K which is the product of the Voltage Controlled Oscillator (VCO), Phase Detector (PD) and divider gains. One unknown variable can be then determined via a single equation, that can be derived at a single frequency. The measurement of a low frequency modulated single tone, for example, is sufficient to characterize the entire PLL TF.
摘要翻译：提供了一种用于实现SigmaDelta分数PLL的有效调制补偿的技术。 PLL TF的参数是PLL的增益Kpll和与环路滤波器相关联的时间常数。 PLL的仔细设计允许将PLL TF的极点和零点设置为固定值，与过程和温度无关。然后将系统的未知参数简化为一个：PLL增益，K是压控振荡器（VCO），相位检测器（PD）和分频器增益的乘积。可以通过单个方程来确定一个未知变量，这可以在单个频率下得到。例如，低频调制单音的测量足以表征整个PLL TF。

3. 发明授权

US07315601B2 Low-noise sigma-delta frequency synthesizer 有权
标题翻译：低噪声Σ-Δ频率合成器
公开(公告)号：US07315601B2
公开(公告)日：2008-01-01
申请号：US10387848
申请日：2003-03-13
申请人： Paul H. Fontaine , Abdellatif Bellaouar , Bertan Bakkaloglu
发明人： Paul H. Fontaine , Abdellatif Bellaouar , Bertan Bakkaloglu
IPC分类号： H03D3/24 , H03L7/06
CPC分类号： H03L7/091 , H03L7/1976
摘要： A sample-and-hold (SAH) phase detector (PD) is clocked in such a way (using a reverse clocking mode) so as to avoid quantization noise increases due to folding that is generally associated with conventional charge pump based phase detectors. The PD is clocked with a clean clock (reference clock), rather than a divided clock. The SAH PD architecture additionally includes an integrated filtering function.
摘要翻译：采样和保持（SAH）相位检测器（PD）以这种方式（使用反向时钟模式）被计时，以避免由于通常与常规基于电荷泵的相位检测器相关联的折叠引起的量化噪声增加。 PD使用干净的时钟（参考时钟）来计时，而不是分时钟。 SAH PD架构还包括集成滤波功能。

4. 发明授权

US07440491B2 Ultra-wideband communications system devices 有权
标题翻译：超宽带通信系统设备
公开(公告)号：US07440491B2
公开(公告)日：2008-10-21
申请号：US10759480
申请日：2004-01-16
申请人： Jaiganesh Balakrishnan , Anuj Batra , Anand G. Dabak , Abdellatif Bellaouar , Paul H. Fontaine , Michel Frechette , Ranjit Gharpurey , Heng-Chih Lin
发明人： Jaiganesh Balakrishnan , Anuj Batra , Anand G. Dabak , Abdellatif Bellaouar , Paul H. Fontaine , Michel Frechette , Ranjit Gharpurey , Heng-Chih Lin
IPC分类号： H04B1/00
CPC分类号： H04B1/719 , H04B1/71635 , H04B1/71637
摘要： System for ultra-wideband communications providing high data rates over an extended operating range in the presence of interferers. A preferred embodiment comprises an ultra-wideband (UWB) device that makes use of a portion of the UWB frequency range to help provide good performance in the presence of interferers. Additionally, since only a portion of the UWB frequency range is used, multiple devices can simultaneously transmit and receive by using different portions of the UWB frequency range.
摘要翻译：用于在存在干扰源的情况下在扩展工作范围内提供高数据速率的超宽带通信系统。优选实施例包括利用UWB频率范围的一部分来帮助在存在干扰源的情况下提供良好性能的超宽带（UWB）设备。此外，由于仅使用UWB频率范围的一部分，所以多个设备可以通过使用UWB频率范围的不同部分同时发送和接收。

5. 发明授权

US06856174B1 Versatile system for high resolution device calibration 有权
标题翻译：用于高分辨率器件校准的多功能系统
公开(公告)号：US06856174B1
公开(公告)日：2005-02-15
申请号：US10677105
申请日：2003-10-01
申请人： Paul H. Fontaine , Abdellatif Bellaouar
发明人： Paul H. Fontaine , Abdellatif Bellaouar
IPC分类号： G01R31/3167 , H03M1/10 , H03M1/68 , H03K17/00
CPC分类号： H03M1/1014 , G01R31/3167 , H03M1/68
摘要： The present invention provides a system for providing high-resolution calibration of a programmable semiconductor component (518). The system calibrates the programmable semiconductor component, within a desired accuracy, to a goal value (802). The system provides a primary DAC function (510) and a supplemental DAC function (512), as well as a control function (506). The control function is utilized to determine a first bit step (806) of the primary DAC function that corresponds to the goal value. The control function then determines a second bit step (810) of the supplemental DAC function that corresponds to the goal value. The bit codes of the first and second bit steps are combined by a summing function (514), to provide a programming control word for the programmable semiconductor component.
摘要翻译：本发明提供了一种用于提供可编程半导体元件（518）的高分辨率校准的系统。系统将可编程半导体部件以期望的精度校准到目标值（802）。该系统提供初级DAC功能（510）和补充DAC功能（512）以及控制功能（506）。控制功能用于确定与目标值对应的初级DAC功能的第一位步骤（806）。然后，控制功能确定对应于目标值的补充DAC功能的第二位步骤（810）。通过加法函数（514）将第一和第二位步骤的位代码组合，以提供可编程半导体部件的编程控制字。

6. 发明授权

US07756002B2 Time-frequency interleaved orthogonal frequency division multiplexing ultra wide band physical layer 有权
标题翻译：时频交织正交频分复用超宽带物理层
公开(公告)号：US07756002B2
公开(公告)日：2010-07-13
申请号：US10688169
申请日：2003-10-18
申请人： Anuj Batra , Jaiganesh Balakrishnan , Anand G. Dabak , Ranjit Gharpurey , Paul H. Fontaine , Heng-Chih Lin
发明人： Anuj Batra , Jaiganesh Balakrishnan , Anand G. Dabak , Ranjit Gharpurey , Paul H. Fontaine , Heng-Chih Lin
IPC分类号： H04J11/00
CPC分类号： H04B1/7163 , H04L1/0041 , H04L1/0069 , H04L1/0071 , H04L1/0075 , H04L27/2602
摘要： A PHY entity for a UWB system utilizes the unlicensed 3.1-10.6 GHZ UWB band, as regulated in the United States by the Code of Federal Regulation, Title 47, Section 15. The UWB system provides a wireless pico area network (PAN) with data payload communication capabilities of 55, 80, 110, 160, 200, 320 and 480 Mb/s. The UWB system employs orthogonal frequency division multiplexing (OFDM) and uses a total of 122 sub-carriers that are modulated using quadrature phase shift keying (QPSK). Forward error correction coding (convolutional coding) is used with a coding rate of 11/32, 1/2, 5/8 and 3/4.
摘要翻译： UWB系统的PHY实体利用美国由“联邦法规”第47章第15节规定的未经授权的3.1-10.6 GHZ UWB频带。UWB系统提供无线微微区域网络（PAN）与数据有效载荷通信能力为55,80,110,160,200,320和480 Mb / s。 UWB系统采用正交频分复用（OFDM），并且使用使用正交相移键控（QPSK）调制的总共122个子载波。前向纠错编码（卷积编码）的编码率为11/32，1/2，5/8和3/4。

7. 发明申请

US20070229159A1 Multi-mode class-D amplifiers 审中-公开
标题翻译：多模D类放大器
公开(公告)号：US20070229159A1
公开(公告)日：2007-10-04
申请号：US11728883
申请日：2007-03-27
申请人： Jagadeesh Krishnan , Paul H. Fontaine
发明人： Jagadeesh Krishnan , Paul H. Fontaine
IPC分类号： H03F3/45
CPC分类号： H03F3/217 , H03F1/32 , H03F3/2173 , H03F3/45475 , H03F2200/331 , H03F2200/351 , H03F2203/45594
摘要： Multi-mode class-D amplifiers are disclosed. An example multi-mode class-D amplifier circuit having an analog input and a digital input disclosed herein comprises a single-mode class-D amplifier having an amplifier input, a smoothing filter having a filter input and a filter output, wherein the filter output is electronically coupled to the amplifier input, and a multiplexer electronically coupled to the filter input to select between at least one of the analog input and the digital input of the multi-mode class-D amplifier circuit.
摘要翻译：公开了多模D类放大器。具有本文公开的模拟输入和数字输入的示例性多模D类放大器电路包括具有放大器输入的单模D类放大器，具有滤波器输入和滤波器输出的平滑滤波器，其中滤波器输出电子耦合到放大器输入，以及多路复用器，电连接到滤波器输入端，以在多模D类放大器电路的模拟输入和数字输入中的至少一个之间进行选择。

8. 发明授权

US06563448B1 Flexible sample rate converter for multimedia digital-to-analog conversion in a wireless telephone 有权
标题翻译：灵活的采样率转换器，用于无线电话中的多媒体数模转换
公开(公告)号：US06563448B1
公开(公告)日：2003-05-13
申请号：US10135354
申请日：2002-04-29
申请人： Paul H. Fontaine
发明人： Paul H. Fontaine
IPC分类号： H03M300
CPC分类号： H03H17/0642 , H03H17/0614 , H03H17/0685 , H03M3/508
摘要： A wireless telephone (40) is disclosed, in which audio input/output circuitry (44) includes a digital-to-analog conversion function (50) for producing an analog output signal (s(t)) based upon a digital baseband signal (S) from a digital signal processor (42). The digital-to-analog conversion function (50) includes first and second &Sgr;&Dgr; modulators (46, 48), each of which are controlled by a sampling clock generated by a dual frequency divider (47) controlled by the first &Sgr;&Dgr; modulator (46). A sampling latch (49) samples the digital baseband signal synchronously with the sampling clock. The second &Sgr;&Dgr; modulator (48) selects an oversampling multiple that is applied to a digit filter (52) along with the sampled signal from the sampling latch (49). The digital filter (52) reconstructs a digital signal from the sampled value and the oversampling multiple that is the equivalent of that reconstructed by the decimation of an over sampled signal. The reconstructed signal is converted to analog by a digital-to-analog converter (56). However, the digital filter (52) and DAC (56) can operate at a much lower frequency than in conventional circuits, thus providing excellent noise performance without requiring high frequency clocking.
摘要翻译：公开了一种无线电话（40），其中音频输入/输出电路（44）包括用于基于数字基带信号（s（t））产生模拟输出信号（s（t））的数模转换功能（50） S）从数字信号处理器（42）发送。数模转换功能（50）包括第一和第二SIGMADELTA调制器（46,48），每个调制器由由第一SIGMADELTA调制器（46）控制的双分频器（47）产生的采样时钟控制，。采样锁存器（49）与采样时钟同步采样数字基带信号。第二SIGMADELTA调制器（48）选择与来自采样锁存器（49）的采样信号一起施加到数字滤波器（52）的过采样倍数。数字滤波器（52）根据采样值和过采样倍数重建数字信号，该采样倍数等于通过抽取过采样信号而重构的数字信号。重建的信号由数模转换器（56）转换为模拟信号。然而，数字滤波器（52）和DAC（56）可以以比常规电路低得多的频率工作，从而提供优异的噪声性能而不需要高频率定时。

9. 发明申请

US20090097178A1 METHODS AND APPARATUS TO DETECT AND OVER-CURRENT IN SWITCHING CIRCUITS 审中-公开
标题翻译：在开关电路中检测和过流的方法和装置
公开(公告)号：US20090097178A1
公开(公告)日：2009-04-16
申请号：US11871691
申请日：2007-10-12
申请人： Jagadeesh Krishnan , Angelo W. Pereira , Rajkumar Jayaraman , Paul H. Fontaine
发明人： Jagadeesh Krishnan , Angelo W. Pereira , Rajkumar Jayaraman , Paul H. Fontaine
IPC分类号： H02H3/08
CPC分类号： H03F3/2173 , H03F1/523 , H03F3/2171
摘要： Methods and apparatus to detect an over-current in switching circuits are described. An example method to detect an over-current in a switching circuit includes randomly selecting a sensor from a plurality of sensors operatively coupled to an output stage of the switching circuit; detecting a first voltage via the randomly selected sensor; and comparing the first voltage to a reference voltage to generate a signal, wherein the signal indicates a status of the output stage of the switching circuit.
摘要翻译：描述了检测开关电路中的过电流的方法和装置。检测开关电路中的过电流的示例性方法包括从可操作地耦合到开关电路的输出级的多个传感器中随机选择传感器; 经由随机选择的传感器检测第一电压; 以及将所述第一电压与参考电压进行比较以产生信号，其中所述信号指示所述开关电路的输出级的状态。

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