专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07550380B2 Electroless plating of metal caps for chalcogenide-based memory devices 有权
标题翻译：用于基于硫族化物的存储器件的金属盖的无电镀
公开(公告)号：US07550380B2
公开(公告)日：2009-06-23
申请号：US11668107
申请日：2007-01-29
申请人： Patricia C. Elkins , John T. Moore , Rita J. Klein
发明人： Patricia C. Elkins , John T. Moore , Rita J. Klein
IPC分类号： H01L21/44
CPC分类号： H01L21/288 , H01L21/76849 , H01L21/76877 , H01L45/085 , H01L45/1233 , H01L45/143 , H01L45/16
摘要： A method of forming a metal cap over a conductive interconnect in a chalcogenide-based memory device is provided and includes, forming a layer of a first conductive material over a substrate, depositing an insulating layer over the first conductive material and the substrate, forming an opening in the insulating layer to expose at least a portion of the first conductive material, depositing a second conductive material over the insulating layer and within the opening, removing portions of the second conductive material to form a conductive area within the opening, recessing the conductive area within the opening to a level below an upper surface of the insulating layer, forming a cap of a third conductive material over the recessed conductive area within the opening, depositing a stack of a chalcogenide based memory cell material over the cap, and depositing a conductive material over the chalcogenide stack.
摘要翻译：提供了一种在基于硫族化物的存储器件中在导电互连上形成金属帽的方法，包括：在衬底上形成第一导电材料层，在第一导电材料和衬底上沉积绝缘层，形成在所述绝缘层中开口以露出所述第一导电材料的至少一部分，在所述绝缘层上并在所述开口内沉积第二导电材料，去除所述第二导电材料的部分以在所述开口内形成导电区域，使所述导电在所述开口内的所述绝缘层的上表面以下的水平面上，在所述开口内的所述凹入的导电区域上形成第三导电材料的盖，在所述盖上沉积基于硫属元素化物的存储单元材料的堆叠，导电材料在硫族化物堆上。

2. 发明授权

US07189626B2 Electroless plating of metal caps for chalcogenide-based memory devices 失效
标题翻译：用于基于硫族化物的存储器件的金属盖的无电镀
公开(公告)号：US07189626B2
公开(公告)日：2007-03-13
申请号：US10980658
申请日：2004-11-03
申请人： Patricia C. Elkins , John T. Moore , Rita J. Klein
发明人： Patricia C. Elkins , John T. Moore , Rita J. Klein
IPC分类号： H01L21/20
CPC分类号： H01L21/288 , H01L21/76849 , H01L21/76877 , H01L45/085 , H01L45/1233 , H01L45/143 , H01L45/16
摘要： A method of forming a metal cap over a conductive interconnect in a chalcogenide-based memory device is provided and includes, forming a layer of a first conductive material over a substrate, depositing an insulating layer over the first conductive material and the substrate, forming an opening in the insulating layer to expose at least a portion of the first conductive material, depositing a second conductive material over the insulating layer and within the opening, removing portions of the second conductive material to form a conductive area within the opening, recessing the conductive area within the opening to a level below an upper surface of the insulating layer, forming a cap of a third conductive material over the recessed conductive area within the opening, the third conductive material selected from the group consisting of cobalt, silver, gold, copper, nickel, palladium, platinum, and alloys thereof, depositing a stack of a chalcogenide based memory cell material over the cap, and depositing a conductive material over the chalcogenide stack.
摘要翻译：提供了一种在基于硫族化物的存储器件中在导电互连上形成金属帽的方法，包括：在衬底上形成第一导电材料层，在第一导电材料和衬底上沉积绝缘层，形成在所述绝缘层中开口以露出所述第一导电材料的至少一部分，在所述绝缘层上并在所述开口内沉积第二导电材料，去除所述第二导电材料的部分以在所述开口内形成导电区域，使所述导电在所述开口内的所述绝缘层的上表面以下的层，在所述开口内的所述凹陷导电区域上形成第三导电材料的盖，所述第三导电材料选自钴，银，金，铜，镍，钯，铂及其合金，在高温下沉积基于硫族化物的记忆电池材料的堆叠 p，并在硫族化物堆叠上沉积导电材料。

3. 发明授权

US08058130B2 Method of forming a nitrogen-enriched region within silicon-oxide-containing masses 有权
标题翻译：在含氧化硅的质量块内形成富氮区的方法
公开(公告)号：US08058130B2
公开(公告)日：2011-11-15
申请号：US12196988
申请日：2008-08-22
申请人： Gurtej S. Sandhu , John T. Moore , Neal R. Rueger
发明人： Gurtej S. Sandhu , John T. Moore , Neal R. Rueger
IPC分类号： H01L21/00
CPC分类号： H01L21/02332 , H01L21/0234 , H01L21/265 , H01L21/28061 , H01L21/28167 , H01L21/28185 , H01L21/28202 , H01L21/3144 , H01L29/513 , H01L29/518 , H01L29/6659 , H01L29/7833
摘要： The invention encompasses a method of incorporating nitrogen into a silicon-oxide-containing layer. The silicon-oxide-containing layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer. The nitrogen is subsequently thermally annealed within the layer to bond at least some of the nitrogen to silicon within the layer. The invention also encompasses a method of forming a transistor. A gate oxide layer is formed over a semiconductive substrate. The gate oxide layer comprises silicon dioxide. The gate oxide layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer, and the layer is maintained at less than or equal to 400° C. during the exposing. Subsequently, the nitrogen within the layer is thermally annealed to bond at least a majority of the nitrogen to silicon. At least one conductive layer is formed over the gate oxide layer. Source/drain regions are formed within the semiconductive substrate, and are gatedly connected to one another by the at least one conductive layer. The invention also encompasses transistor structures.
摘要翻译：本发明包括将氮掺入含氧化硅的层中的方法。将含氧化硅的层暴露于含氮等离子体中以将氮引入层中。氮气随后在层内热退火以将至少一些氮与硅结合在层内。本发明还包括形成晶体管的方法。在半导体衬底上形成栅氧化层。栅氧化层包括二氧化硅。将栅极氧化层暴露于含氮等离子体中以将氮引入层中，并且在暴露期间该层保持在小于或等于400℃。随后，层内的氮被热退火以将至少大部分氮与硅结合。在栅极氧化物层上形成至少一个导电层。源极/漏极区域形成在半导体衬底内，并且通过至少一个导电层彼此门控连接。本发明还包括晶体管结构。

4. 发明申请

US20080225579A1 MEMORY ARCHITECTURE AND METHOD OF MANUFACTURE AND OPERATION THEREOF 有权
标题翻译：存储器结构及其制造和操作方法
公开(公告)号：US20080225579A1
公开(公告)日：2008-09-18
申请号：US12110532
申请日：2008-04-28
申请人： John T. Moore , Terry L. Gilton
发明人： John T. Moore , Terry L. Gilton
IPC分类号： G11C11/00 , G11C7/00 , G11C8/00 , H01L21/00
CPC分类号： G11C13/003 , G11C5/063 , G11C7/18 , G11C11/4097 , G11C13/0011 , G11C13/004 , G11C2213/75 , G11C2213/76 , G11C2213/79 , H01L27/0203 , H01L27/105 , H01L27/1052
摘要： An architecture, and its method of formation and operation, containing a high density memory array of semi-volatile or non-volatile memory elements, including, but not limited to, programmable conductive access memory elements. The architecture in one exemplary embodiment has a pair of semi-volatile or non-volatile memory elements which selectively share a bit line through respective first electrodes and access transistors controlled by respective word lines. The memory elements each have a respective second electrode coupled thereto which in cooperation with the bit line access transistors and first electrode, serves to apply read, write and erase signals to the memory element.
摘要翻译：一种架构及其形成和操作方法，其包含半易失性或非易失性存储器元件的高密度存储器阵列，包括但不限于可编程导电存取存储器元件。一个示例性实施例中的架构具有一对半挥发性或非易失性存储器元件，其通过相应的第一电极和由相应字线控制的存取晶体管选择性地共享位线。存储元件各自具有耦合到其上的相应的第二电极，其与位线存取晶体管和第一电极协作，用于向存储元件施加读取，写入和擦除信号。

5. 发明授权

US07385868B2 Method of refreshing a PCRAM memory device 有权
标题翻译：刷新PCRAM存储器件的方法
公开(公告)号：US07385868B2
公开(公告)日：2008-06-10
申请号：US11128177
申请日：2005-05-13
申请人： John T. Moore , Terry L. Gilton , Kristy A. Campbell
发明人： John T. Moore , Terry L. Gilton , Kristy A. Campbell
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C11/406 , G11C11/40622 , G11C13/0004 , G11C13/0011 , G11C13/0033 , G11C16/3431 , G11C2211/4065 , G11C2211/4068 , G11C2213/79
摘要： A method for refreshing PCRAM cells programmed to a low resistance state and entire arrays of PCRAM cells uses a simple refresh scheme which does not require separate control and application of discrete refresh voltages to the PCRAM cells in an array. Specifically, the array structure of a PCRAM device is constructed to allow leakage current to flow through each programmed cell in the array to refresh the programmed state. In one embodiment, the leakage current flows across the access device between the anode of the memory element and the bit line to which the cell is connected, for each memory cell in the array which has been programmed to the low resistance state. In another embodiment, the leakage current flows to the programmed cells through a doped substrate or doped regions of a substrate on which each cell is formed. An entire array is refreshed simultaneously by forming each memory element in the array to have one common anode formed as a single cell plate for the array. Only PCRAM cells in the array written to the low resistance state are refreshed by the controlled leakage current, whereas cells in the high resistance state are not affected by the refresh operation.
摘要翻译：用于刷新编程为低电阻状态的PCRAM细胞的方法和PCRAM细胞的整个阵列使用简单的刷新方案，其不需要单独控制并且向阵列中的PCRAM细胞施加离散的刷新电压。具体地，构建PCRAM器件的阵列结构以允许漏电流流过阵列中的每个编程单元以刷新编程状态。在一个实施例中，针对已经被编程为低电阻状态的阵列中的每个存储器单元，漏电流在存储元件的阳极和单元连接的位线之间流过访问设备。在另一个实施例中，漏电流通过其上形成有每个单元的衬底的掺杂衬底或掺杂区流动到编程单元。通过在阵列中形成每个存储元件以使一个共同的阳极形成为阵列的单个单元板，整个阵列同时刷新。写入低电阻状态的阵列中只有PCRAM单元被控制的漏电流刷新，而高电阻状态下的单元不受刷新操作的影响。

6. 发明授权

US07199444B2 Memory device, programmable resistance memory cell and memory array 有权
标题翻译：存储器件，可编程电阻存储单元和存储器阵列
公开(公告)号：US07199444B2
公开(公告)日：2007-04-03
申请号：US11219742
申请日：2005-09-07
申请人： John T. Moore , Terry L. Gilton
发明人： John T. Moore , Terry L. Gilton
IPC分类号： H01L29/12
CPC分类号： H01L45/04 , H01L27/101 , H01L28/24 , H01L45/085 , H01L45/1233 , H01L45/141 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/1658 , H01L45/1675
摘要： A method of metal doping a chalcogenide material includes forming a metal over a substrate. A chalcogenide material is formed on the metal. Irradiating is conducted through the chalcogenide material to the metal effective to break a chalcogenide bond of the chalcogenide material at an interface of the metal and chalcogenide material and diffuse at least some of the metal outwardly into the chalcogenide material. A method of metal doping a chalcogenide material includes surrounding exposed outer surfaces of a projecting metal mass with chalcogenide material. Irradiating is conducted through the chalcogenide material to the projecting metal mass effective to break a chalcogenide bond of the chalcogenide material at an interface of the projecting metal mass outer surfaces and diffuse at least some of the projecting metal mass outwardly into the chalcogenide material. In certain aspects, the above implementations are incorporated in methods of forming non-volatile resistance variable devices. In one implementation, a non-volatile resistance variable device in a highest resistance state for a given ambient temperature and pressure includes a resistance variable chalcogenide material having metal ions diffused therein. Opposing first and second electrodes are received operatively proximate the resistance variable chalcogenide material. At least one of the electrodes has a conductive projection extending into the resistance variable chalcogenide material.
摘要翻译：金属掺杂硫族化物材料的方法包括在衬底上形成金属。在金属上形成硫族化物材料。通过硫属化物材料对金属进行辐射，有效地在金属和硫族化物材料的界面处破坏硫族化物材料的硫族化物键，并将至少一些金属向外扩散到硫族化物材料中。金属掺杂硫族化物材料的方法包括用硫族化物材料包围突出的金属块的暴露的外表面。通过硫族化物材料将辐射照射到突出金属质量块上，有效地在突出的金属质量外表面的界面处破坏硫族化物材料的硫族化物键，并将至少一些突出的金属块向外扩散到硫族化物材料中。在某些方面，上述实施方式被并入形成非易失性电阻可变器件的方法中。在一个实施方案中，对于给定的环境温度和压力，最高电阻状态的非易失性电阻可变器件包括在其中扩散有金属离子的电阻变化硫属化物材料。反向的第一和第二电极在电阻可变硫属化物材料上可操作地接收。至少一个电极具有延伸到电阻可变硫族化物材料中的导电突起。

7. 发明授权

US07157778B2 Semiconductor constructions 有权
标题翻译：半导体结构
公开(公告)号：US07157778B2
公开(公告)日：2007-01-02
申请号：US11018848
申请日：2004-12-20
申请人： John T. Moore
发明人： John T. Moore
IPC分类号： H01L29/76 , H01L31/062
CPC分类号： H01L21/823462 , H01L21/3145 , H01L21/31612
摘要： The invention encompasses a method of forming an oxide region over a semiconductor substrate. A nitrogen-containing layer is formed across at least some of the substrate. After the nitrogen-containing layer is formed, an oxide region is grown from at least some of the substrate. The nitrogen of the nitrogen-containing layer is dispersed within the oxide region. The invention also encompasses a method of forming a pair of transistors associated with a semiconductor substrate. A substrate is provided. A first region of the substrate is defined, and additionally a second region of the substrate is defined. A first oxide region is formed which covers at least some of the first region of the substrate, and which does not cover any of the second region of the substrate. A nitrogen-comprising layer is formed across at least some of the first oxide region and across at least some of the second region of the substrate. After the nitrogen-comprising layer is formed, a second oxide region is grown from the second region of the substrate. A first transistor gate is formed over the first oxide region, and a second transistor gate is formed over the second oxide region.
摘要翻译：本发明包括在半导体衬底上形成氧化物区域的方法。在至少一些基底上形成含氮层。在形成含氮层之后，从衬底中的至少一些生长氧化物区域。含氮层的氮分散在氧化物区域内。本发明还包括形成与半导体衬底相关联的一对晶体管的方法。提供基板。限定衬底的第一区域，并且另外定义衬底的第二区域。形成第一氧化物区域，其覆盖衬底的第一区域中的至少一些，并且不覆盖衬底的任何第二区域。跨越第一氧化物区域中的至少一些并穿过衬底的至少一些第二区域形成含氮层。在形成含氮层之后，从衬底的第二区域生长第二氧化物区域。在第一氧化物区域上形成第一晶体管栅极，在第二氧化物区域上形成第二晶体管栅极。

8. 发明授权

US07151273B2 Silver-selenide/chalcogenide glass stack for resistance variable memory 失效
标题翻译：用于电阻变量记忆的硒化银/硫族化物玻璃堆叠
公开(公告)号：US07151273B2
公开(公告)日：2006-12-19
申请号：US10120521
申请日：2002-04-12
申请人： Kristy A. Campbell , John T. Moore
发明人： Kristy A. Campbell , John T. Moore
IPC分类号： H01L29/04
CPC分类号： G11C13/0011 , G11C2213/51 , G11C2213/56 , H01L45/085 , H01L45/1233 , H01L45/143 , H01L45/1616 , H01L45/1625
摘要： The invention is related to methods and apparatus for providing a resistance variable memory element with improved data retention and switching characteristics. According to an embodiment of the invention a resistance variable memory element is provided having at least one silver-selenide layer in between glass layers, wherein at least one of the glass layers is a chalcogenide glass, preferably having a GexSe100−x composition.
摘要翻译：本发明涉及用于提供具有改进的数据保持和切换特性的电阻可变存储元件的方法和装置。根据本发明的实施例，提供了一种电阻可变存储元件，其在玻璃层之间具有至少一个硒化银层，其中至少一个玻璃层是硫族化物玻璃，优选具有Ge x 100＆lt; 100＆lt; 100＆gt;组合物。

9. 发明授权

US07141850B2 Gated semiconductor assemblies and methods of forming gated semiconductor assemblies 有权
标题翻译：门控半导体组件和形成门控半导体组件的方法
公开(公告)号：US07141850B2
公开(公告)日：2006-11-28
申请号：US10769573
申请日：2004-01-30
申请人： Mark A. Helm , Mark Fischer , John T. Moore , Scott Jeffrey DeBoer
发明人： Mark A. Helm , Mark Fischer , John T. Moore , Scott Jeffrey DeBoer
IPC分类号： H01L29/792
CPC分类号： H01L29/7881 , H01L21/28273 , H01L29/511
摘要： In one aspect, the invention includes a method of forming a gated semiconductor assembly, comprising: a) forming a silicon nitride layer over and against a floating gate; and b) forming a control gate over the silicon nitride layer. In another aspect, the invention includes a method of forming a gated semiconductor assembly, comprising: a) forming a floating gate layer over a substrate; b) forming a silicon nitride layer over the floating gate layer, the silicon nitride layer comprising a first portion and a second portion elevationally displaced from the first portion, the first portion having a greater stoichiometric amount of silicon than the second portion; and c) forming a control gate over the silicon nitride layer. In yet another aspect, the invention includes a gated semiconductor assembly comprising: a) a substrate; b) a floating gate over the substrate; c) a control gate over the floating gate; and d) an electron barrier layer between the floating gate and the control gate, the electron barrier layer comprising a silicon nitride layer, the silicon nitride layer comprising a first portion and a second portion elevationally displaced from the first portion, the first portion having a greater stoichiometric amount of silicon than the second portion.
摘要翻译：一方面，本发明包括一种形成门控半导体组件的方法，包括：a）在浮动栅极上形成氮化硅层; 以及b）在所述氮化硅层上形成控制栅极。另一方面，本发明包括形成门控半导体组件的方法，包括：a）在衬底上形成浮栅; b）在所述浮栅上形成氮化硅层，所述氮化硅层包括从所述第一部分向前倾斜的第一部分和第二部分，所述第一部分具有比所述第二部分更大的化学计量的硅量; 以及c）在所述氮化硅层上形成控制栅极。在另一方面，本发明包括门控半导体组件，其包括：a）衬底; b）衬底上的浮栅; c）浮动门上的控制门; 以及d）在所述浮动栅极和所述控制栅极之间的电子势垒层，所述电子势垒层包括氮化硅层，所述氮化硅层包括第一部分和从所述第一部分向上偏移的第二部分，所述第一部分具有比第二部分更大的化学计量的硅。

10. 发明授权

US07115504B2 Method of forming electrode structure for use in an integrated circuit 有权
标题翻译：形成用于集成电路的电极结构的方法
公开(公告)号：US07115504B2
公开(公告)日：2006-10-03
申请号：US10873230
申请日：2004-06-23
申请人： John T. Moore , Joseph F. Brooks
发明人： John T. Moore , Joseph F. Brooks
IPC分类号： H01L21/44
CPC分类号： H01L24/05 , G11C13/0011 , G11C2213/79 , H01L21/76823 , H01L21/76838 , H01L21/76867 , H01L24/03 , H01L45/085 , H01L45/124 , H01L45/143 , H01L45/1658 , H01L45/1683 , H01L2224/05006 , H01L2224/05546 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01028 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/01057 , H01L2924/01074 , H01L2924/01082 , H01L2924/05042 , H01L2924/13091 , H01L2924/14 , H01L2924/19043 , H01L2924/3011 , Y10S438/957 , H01L2924/00
摘要： An electrode structure includes a first layer of conductive material and a dielectric layer formed on a surface of the first layer. An opening is formed in the dielectric layer to expose a portion of the surface of the first layer. A binding layer is formed on the dielectric layer and on the exposed portion of the surface of the first layer and a second layer of conductive material is formed on the conductive binding layer. The binding layer can be an oxide and the second layer a conductive material that is diffusible into an oxide. The electrode structure can be annealed to cause conductive material from the second layer to be chemisorbed into the binding layer to improve adhesion between the first and second layers. A programmable cell can be formed by forming a doped glass layer in the electrode structure.
摘要翻译：电极结构包括第一层导电材料和形成在第一层表面上的电介质层。在电介质层中形成开口以露出第一层表面的一部分。在电介质层上和第一层的表面的暴露部分上形成粘合层，并且在导电结合层上形成第二导电材料层。结合层可以是氧化物，第二层是可扩散到氧化物中的导电材料。可以将电极结构退火以使来自第二层的导电材料被化学吸附到结合层中，以改善第一和第二层之间的粘附。可以通过在电极结构中形成掺杂的玻璃层来形成可编程单元。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式