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    • 9. 发明申请
    • Scalable Periphery for Digital Power Control
    • 数字电源控制的可扩展外设
    • US20150028953A1
    • 2015-01-29
    • US13948756
    • 2013-07-23
    • Peregrine Semiconductor Corporation
    • David Kovac
    • H03F3/26H03F3/45
    • H03F1/0261H03F1/0277H03F1/223H03F3/193H03F3/211H03F3/245H03F3/72H03F2200/15H03F2203/7236
    • A scalable periphery digital power control arrangement is presented. The scalable periphery digital power control arrangement comprises a plurality of PMOS transistors connected in parallel, where the plurality of transistors is operatively coupled to a voltage source. The plurality of PMOS transistors that is operatively coupled to the voltage source can operate as a controlled current source. Current flow from the voltage source can be controlled by a logic circuit, which sends a logic signal to enable or disable each individual PMOS transistor of the plurality of PMOS transistors connected in parallel. As more PMOS transistors are enabled, the current flow through the scalable periphery digital power control arrangement to the amplifier can increase.
    • 提出了一种可扩展的外围数字功率控制装置。 可扩展的周边数字功率控制装置包括并联连接的多个PMOS晶体管,其中多个晶体管可操作地耦合到电压源。 可操作地耦合到电压源的多个PMOS晶体管可以作为受控电流源工作。 来自电压源的电流可以由逻辑电路来控制,该逻辑电路发送逻辑信号以使能或禁用并联连接的多个PMOS晶体管的各个PMOS晶体管。 随着更多的PMOS晶体管被使能,可以增加通过可扩展外围数字功率控制装置到放大器的电流。