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    • 3. 发明授权
    • Integrated circuits and methods for their fabrication
    • 集成电路及其制造方法
    • US06740582B2
    • 2004-05-25
    • US10133595
    • 2002-04-26
    • Oleg Siniaguine
    • Oleg Siniaguine
    • H01L214763
    • H01L21/441H01L21/304H01L21/3065H01L21/76898H01L23/481H01L23/482H01L25/0657H01L25/50H01L29/0657H01L2224/0401H01L2224/0557H01L2224/05572H01L2224/13025H01L2225/06513H01L2225/06541H01L2225/06593H01L2924/0002H01L2924/014H01L2924/14H01L2924/00012H01L2224/05552
    • To fabricate back side contact pads that are suitable for use in a vertical integrated circuit, vias are made in the face side of a wafer, and dielectric and contact pad metal are deposited into the vias. Then the wafer back side is etched until the metal is exposed. When the etch exposes the insulator at the via bottoms, the insulator is etched slower than the wafer material (e.g. silicon). Therefore, when the dielectric is etched off and the metal is exposed, the dielectric protrudes down from the wafer back side around the exposed metal contact pads, by about 8 &mgr;m in some embodiments. The protruding dielectric portions improve insulation between the wafer and the contact pads when the contact pads are soldered to an underlying circuit. In some embodiments, before the contact pads are soldered, additional dielectric is grown on the wafer back side without covering the contact pads. In some embodiments, the wafer etch and the fabrication of the additional dielectric are performed one after another by a plasma process while the wafer is held in a non-contact wafer holder. In some embodiments, the wafer is diced and the dice are tested before the etch. The etch and the deposition of the additional dielectric are performed on good dice only. In some embodiments, the dice are not used for vertical integration.
    • 为了制造适合于在垂直集成电路中使用的背面接触焊盘,在晶片的正面侧形成通孔,并且将电介质和接触垫金属沉积到通孔中。 然后蚀刻晶片背面,直到金属露出。 当蚀刻在通孔底部暴露绝缘体时,绝缘体被蚀刻比晶片材料(例如硅)慢。 因此,当电介质被蚀刻并且金属被暴露时,在一些实施例中,电介质从暴露的金属接触焊盘周围的晶片背面向下突出大约8μm。 当接触焊盘焊接到底层电路时,突出的电介质部分改善晶片和接触焊盘之间的绝缘。 在一些实施例中,在接触焊盘被焊接之前,在晶片背面上生长附加电介质,而不覆盖接触焊盘。 在一些实施例中,当晶片保持在非接触晶片保持器中时,通过等离子体处理一个接一个地执行晶片蚀刻和附加电介质的制造。 在一些实施例中,切割晶片,并且在蚀刻之前测试晶片。 附加电介质的蚀刻和沉积仅在良好的骰子上进行。 在一些实施例中,骰子不用于垂直整合。
    • 6. 发明授权
    • Integrated circuits and methods for their fabrication
    • 集成电路及其制造方法
    • US06184060B2
    • 2001-02-06
    • US09083927
    • 1998-05-22
    • Oleg Siniaguine
    • Oleg Siniaguine
    • H01L2148
    • H01L21/441H01L21/304H01L21/3065H01L21/76898H01L23/481H01L23/482H01L25/0657H01L25/50H01L29/0657H01L2224/0401H01L2224/0557H01L2224/05572H01L2224/13025H01L2225/06513H01L2225/06541H01L2225/06593H01L2924/0002H01L2924/014H01L2924/14H01L2924/00012H01L2224/05552
    • To fabricate back side contact pads that are suitable for use in a vertical integrated circuit, vias are made in the face side of a wafer, and dielectric and contact pad metal are deposited into the vias. Then the wafer back side is etched until the metal is exposed. When the etch exposes the insulator at the via bottoms, the insulator is etched slower than the wafer material (e.g. silicon). Therefore, when the dielectric is etched off and the metal is exposed, the dielectric protrudes down from the wafer back side around the exposed metal contact pads, by about 8 &mgr;m in some embodiments. The protruding dielectric portions improve insulation between the wafer and the contact pads when the contact pads are soldered to an underlying circuit. In some embodiments, before the contact pads are soldered, additional dielectric is grown on the wafer back side without covering the contact pads. In some embodiments, the wafer etch and the fabrication of the additional dielectric are performed one after another by a plasma process while the wafer is held in a non-contact wafer holder. In some embodiments, the wafer is diced and the dice are tested before the etch. The etch and the deposition of the additional dielectric are performed on good dice only. In some embodiments, the dice are not used for vertical integration.
    • 为了制造适合于在垂直集成电路中使用的背面接触焊盘,在晶片的正面侧形成通孔,并且将电介质和接触垫金属沉积到通孔中。 然后蚀刻晶片背面,直到金属露出。 当蚀刻在通孔底部暴露绝缘体时,绝缘体被蚀刻比晶片材料(例如硅)慢。 因此,当电介质被蚀刻并且金属被暴露时,在一些实施例中,电介质从暴露的金属接触焊盘周围的晶片背面向下突出大约8μm。 当接触焊盘焊接到底层电路时,突出的电介质部分改善晶片和接触焊盘之间的绝缘。 在一些实施例中,在接触焊盘被焊接之前,在晶片背面上生长附加电介质,而不覆盖接触焊盘。 在一些实施例中,当晶片保持在非接触晶片保持器中时,通过等离子体处理一个接一个地执行晶片蚀刻和附加电介质的制造。 在一些实施例中,切割晶片,并且在蚀刻之前测试晶片。 附加电介质的蚀刻和沉积仅在良好的骰子上进行。 在一些实施例中,骰子不用于垂直整合。