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1. 发明授权

US5203997A Hydrophilic porous membrane, method of manufacturing the same and liquid filter using the same 失效
标题翻译：亲水多孔膜，其制造方法和使用其的液体过滤器
公开(公告)号：US5203997A
公开(公告)日：1993-04-20
申请号：US345244
申请日：1989-05-01
申请人： Noriyuki Koyama , Shinsuke Yokomati , Yasushi Nemoto , Makoto Ohnishi
发明人： Noriyuki Koyama , Shinsuke Yokomati , Yasushi Nemoto , Makoto Ohnishi
IPC分类号： A61M1/34 , A61M1/22 , B01D67/00 , B01D71/34 , B01D71/52 , B01D71/82 , C08J9/40
CPC分类号： B01D67/0088 , B01D67/0093
摘要： A hydrophilic porous membrane is obtained by covering porous membrane substrate with a non-ionic, amino-acid-based or non-ionic fluorine-based surface active agent. For the covering, the porous membrane substrate is immersed in a solution containing the surface active agent and then drying the membrane substrate. A different hydrophilic porous membrane is obtained by providing the surfaces of a porous membrane substrate and inner pore surfaces with a polar group and then covering the membrane substrate with a hydrophilic polymer film. For this covering, after introduction of the polar group to the surfaces of the porous membrane substrate and inner pore surfaces, the membrane substrate is immersed in a solution containing a hydrophilic substance and then dried. In a liquid filter using any of these hydrophilic porous membrane, the porous membrane is disposed in a housing such as to divide the housing inner space into two sub-spaces respectively communicating with a liquid inlet and a filtrate outlet provided on the housing.

2. 发明授权

US5279856A Hydrophilic porous membrane, method of manufacturing the same and liquid filter using same 失效
标题翻译：亲水性多孔膜，其制造方法和使用其的液体过滤器
公开(公告)号：US5279856A
公开(公告)日：1994-01-18
申请号：US996158
申请日：1992-12-23
申请人： Noriyuki Koyama , Shinsuke Yokomachi , Yasushi Nemoto , Makoto Ohnishi
发明人： Noriyuki Koyama , Shinsuke Yokomachi , Yasushi Nemoto , Makoto Ohnishi
IPC分类号： B01D67/00
CPC分类号： B01D67/0088 , B01D67/0093
摘要： A hydrophilic porous membrane is obtained by covering porous membrane substrate with a non-ionic, amino-acid-based or non-ionic fluorine-based surface active agent. For the covering, the porous membrane substrate is immersed in a solution containing the surface active agent and then drying the membrane substrate. A different hydrophilic porous membrane is obtained by providing the surfaces of a porous membrane substrate and inner pore surfaces with a polar group and then covering the membrane substrate with a hydrophilic polymer film. For this covering, after introduction of the polar group to the surfaces of the porous membrane substrate and inner pore surfaces, the membrane substrate is immersed in a solution containing a hydrophilic substance and then dried. In a liquid filter using any of these hydrophilic porous membrane the porous membrane is disposed in a housing such as to divide the housing inner space into two sub-spaces respectively communicating with a liquid inlet and a filtrate outlet provided on the housing.
摘要翻译：通过用非离子，氨基酸或非离子的氟基表面活性剂覆盖多孔膜基底来获得亲水性多孔膜。对于覆盖物，将多孔膜基材浸渍在含有表面活性剂的溶液中，然后干燥膜基材。通过使多孔膜基材的表面和内孔表面具有极性基团，然后用亲水性聚合物膜覆盖膜基材，获得不同的亲水性多孔膜。对于该覆盖物，在将极性基团引入到多孔膜基材和内孔表面的表面之后，将膜基材浸渍在含有亲水性物质的溶液中，然后干燥。在使用任何这些亲水性多孔膜的液体过滤器中，多孔膜设置在壳体中，以将壳体内部空间分成两个分别与液体入口和设置在壳体上的滤液出口连通的子空间。

3. 发明申请

US20070055847A1 Operational processor with a status information register serving as a data register 审中-公开
标题翻译：具有作为数据寄存器的状态信息寄存器的操作处理器
公开(公告)号：US20070055847A1
公开(公告)日：2007-03-08
申请号：US11515905
申请日：2006-09-06
申请人： Masaru Nagase , Makoto Ohnishi
发明人： Masaru Nagase , Makoto Ohnishi
IPC分类号： G06F9/44
CPC分类号： G06F9/30101 , G06F9/30014 , G06F9/30181 , G06F9/3863
摘要： The operational processor includes a general-purpose register that holds data associated with operation processing, and a program status register that holds information associated with the status of the operational processor. The data and information are saved during interrupt processing or task switching. The program status register holds in its bit positions C1-Cn a portion of data resulting from the operation processing. The held data are the n most significant bits of the least significant bits of the data resulting from the operation processing which are not held in the general-purpose register, and are for use in the operation. The operational processor may perform fewer operations than the double precision operation, and improve the operation precision without increasing the task switching time.
摘要翻译：操作处理器包括保存与操作处理相关联的数据的通用寄存器，以及保存与操作处理器的状态相关联的信息的程序状态寄存器。在中断处理或任务切换期间保存数据和信息。程序状态寄存器的位位置C 1 -C n是由操作处理产生的数据的一部分。所保持的数据是由操作处理产生的数据的最低有效位的n个最高有效位，其不保存在通用寄存器中，并且用于操作。操作处理器可以执行比双精度操作更少的操作，并且在不增加任务切换时间的情况下提高操作精度。

4. 发明授权

US5473280A Modulation/demodulation method and system for realizing quadrature modulation/demodulation technique used in digital mobile radio system with complex signal processing 失效
标题翻译：用于实现具有复杂信号处理的数字移动无线电系统中使用的正交调制/解调技术的调制/解调方法和系统
公开(公告)号：US5473280A
公开(公告)日：1995-12-05
申请号：US198574
申请日：1994-02-18
申请人： Makoto Ohnishi , Masaaki Ohta , Masaru Adachi
发明人： Makoto Ohnishi , Masaaki Ohta , Masaru Adachi
IPC分类号： H04L27/00 , H03C3/40 , H03D3/00 , H04L27/20 , H04L27/22
CPC分类号： H04L27/2092 , H03C3/40 , H03D3/007
摘要： In a complex modulation/demodulation method and system, the data frequency f.sub.C1 of data signals I and Q inputted to a constellation mapping circuit is converted by a digital interpolation circuit into a sampling frequency f.sub.C2 equal to f.sub.S /N, where f.sub.S is an operation sampling frequency and N is selected such that the signal maximum frequency of the data signals I and Q becomes lower than f.sub.C2 /2. The interpolated data signals I and Q are respectively inputted to real and imaginary input terminals of a complex coefficient band pass filter to extract a real signal output. An output signal of the complex coefficient band pass filter is converted by a DA converter into an analog signal from which desired frequency components are extracted by an analog band pass filter, thereby performing a quadrature modulation.
摘要翻译：在复杂的调制/解调方法和系统中，输入到星座映射电路的数据信号I和Q的数据频率fC1被数字内插电路转换成等于fS / N的采样频率fC2，其中fS是操作采样选择频率和N，使得数据信号I和Q的信号最大频率变得低于fC2 / 2。内插数据信号I和Q分别输入到复系数带通滤波器的实和输入端，以提取实信号输出。复数系数带通滤波器的输出信号由DA转换器转换为模拟信号，通过模拟带通滤波器从中提取出期望的频率分量，从而进行正交调制。

5. 发明授权

US5889766A Transmission/reception method based on frequency division multiple access having changeable communication channel bandwidths and communication apparatus employing the method 失效
标题翻译：基于具有可变通信信道带宽的频分多址的发送/接收方法和采用该方法的通信装置
公开(公告)号：US5889766A
公开(公告)日：1999-03-30
申请号：US783200
申请日：1997-01-14
申请人： Makoto Ohnishi , Yukinari Fujiwara
发明人： Makoto Ohnishi , Yukinari Fujiwara
IPC分类号： H04J1/00 , H04B7/26 , H04J1/05 , H04J4/00
CPC分类号： H04B7/2612 , H04J1/05 , H04J4/005
摘要： An FDMA (Frequency-Division Multiple Access) transmitter-receiver for use in an FDMA communication system which is capable of changing a bandwidth of a channel as required. The FDMA transmitter-receiver includes: a plurality of trans-demultiplexers which are different in the number of channel multiplexings from each other and each of which serves to convert the received FDMA signal into a TDMA signal; a communication signal demultiplexing/multiplexing circuit for subjecting the output communication channel signals from the trans-demultiplexers to demultiplex and channel-reassignable multiplex them; a plurality of trans-multiplexers which are provided in correspondence to the plurality of trans-demultiplexers and each of which serves to convert the output channel signal after demultiplexing and remultiplexing from the associated communication signal demultiplexing/multiplexing circuit into an FDMA signal; an adder for adding the FDMA signals outputted from the trans-multiplexers; and a transmission circuit connected to an output of the adder for transmitting therefrom the signal which has been obtained by adding the FDMA signals. The bandwidth per channel of each of the trans-demultiplexers and the trans-multiplexers is different in correspondence to the number of channel multiplexing.
摘要翻译：用于FDMA通信系统的FDMA（频分多址）发射机 - 接收机，其能够根据需要改变频道的带宽。 FDMA发送器 - 接收器包括：多个多路复用器，它们彼此之间的信道多路复用数不同，其中每一个用于将接收的FDMA信号转换成TDMA信号; 通信信号解复用/多路复用电路，用于对来自反多解复用器的输出通信信道信号进行解复用和信道重新分配复用; 多个反复复用器，其对应于多个反解复用器设置，并且其中的每一个用于将解复用后的输出信道信号和从相关联的通信信号解复用电路再复用到FDMA信号中; 加法器，用于将从多路转换器输出的FDMA信号相加; 以及发送电路，连接到加法器的输出端，用于从其中发送通过添加FDMA信号而获得的信号。每个解复用器和多路复用器的每个通道的带宽对应于信道复用的数量是不同的。

6. 发明授权

US4926499A Carrier phase controller for a receiver of phase modulated signals 失效
标题翻译：相位调制信号接收机的载波相位控制器
公开(公告)号：US4926499A
公开(公告)日：1990-05-15
申请号：US122318
申请日：1987-11-18
申请人： Naoya Kobayashi , Makoto Ohnishi , Yoshiro Kokuryo
发明人： Naoya Kobayashi , Makoto Ohnishi , Yoshiro Kokuryo
IPC分类号： H03H15/00 , H04B3/04 , H04L27/00 , H04L27/233 , H04L27/38
CPC分类号： H04L27/2332 , H04L2027/003 , H04L2027/0057 , H04L2027/0069
摘要： A simplified carrier phase control apparatus used in a modem for demodulating a quadrature amplitude modulated data signal, to correct phase jitters of a carrier signal due to a 50 Hz or a 60 Hz frequency of the commercial power supply, and its harmonic wave frequency components. The carrier phase control apparatus has a predictive filter for predicting a carrier phase jitter, the predictive filter composed of band-pass filters with center frequencies of 50 Hz and 60 Hz, and a circuit where the output signals of the band-pass filters are multiplied by the coefficients and added linearly.
摘要翻译：一种在调制解调器中使用的简化的载波相位控制装置，用于解调正交幅度调制数据信号，以校正由商用电源的50Hz或60Hz频率引起的载波信号的相位抖动及其谐波频率分量。载波相位控制装置具有用于预测载波相位抖动的预测滤波器，由中心频率为50Hz和60Hz的带通滤波器组成的预测滤波器以及带通滤波器的输出信号相乘的电路通过系数线性增加。

7. 发明授权

US4285047A Digital adder circuit with a plurality of 1-bit adders and improved carry means 失效
标题翻译：具有多个1位加法器的数字加法器电路和改进的进位装置
公开(公告)号：US4285047A
公开(公告)日：1981-08-18
申请号：US84457
申请日：1979-10-12
申请人： Makoto Ohnishi
发明人： Makoto Ohnishi
IPC分类号： G06F7/504 , G06F7/494 , G06F7/50 , G06F7/508
CPC分类号： G06F7/504
摘要： A digital adder comprises at least two, first and second 1-bit adders; first and second carry circuits which store therein output signals of carry output terminals of said first and second adders and apply them to carry input terminals of said first and second adders, respectively, in response to a predetermined clock signal; first input means for applying each pair of a plurality of pairs of data to be added up and each consisting of a predetermined number of bits, to said first adder in 1-bit sequence from least significant bits of said each pair of data in response to said clock signal; second input means for applying the data to be added to the carry signal delivered from said first adder by the addition of most significant bits of said each pair of data, to said second adder in 1-bit sequence from the least significant bits in response to said clock signal and upon termination of the application of said pair of data to said first adder; a first gate circuit which inhibits the carry signal delivered from said first adder by the addition of the most significant bits of said each pair of data, from being applied to said first carry circuit and applies said carry signal to said second carry circuit; and means for combining outputs of said first and second adders so as to attach the output of said second adder onto a more significant bit side of the output of said first adder and for delivering the combined output as one data.
摘要翻译：数字加法器包括至少两个第一和第二1位加法器; 第一和第二进位电路，其存储所述第一和第二加法器的进位输出端的输出信号，并且分别响应于预定的时钟信号施加它们以携带所述第一和第二加法器的输入端; 第一输入装置，用于响应于所述每对数据的最低有效位，以1比特顺序将每对相加的多对数据对，并且每一对由预定数量的比特组成，所述时钟信号; 第二输入装置，用于通过将所述每对数据的最高有效位相加来将从所述第一加法器传送的进位信号中添加的数据加到所述第二加法器中，以便从最低有效位以1位序列响应于所述时钟信号和在将所述数据对应用于所述第一加法器时终止; 第一门电路，其通过加上所述每对数据的最高有效位来禁止从所述第一加法器传送的进位信号，以将其应用于所述第一进位电路并将所述进位信号施加到所述第二进位电路; 以及用于组合所述第一和第二加法器的输出以便将所述第二加法器的输出附加到所述第一加法器的输出的更有效位侧并用于将组合输出作为一个数据传送的装置。

8. 发明授权

US5926065A Digital modulator having a digital filter including low-speed circuit components 失效
标题翻译：具有包括低速电路元件的数字滤波器的数字调制器
公开(公告)号：US5926065A
公开(公告)日：1999-07-20
申请号：US947348
申请日：1997-10-08
申请人： Hirotake Wakai , Makoto Ohnishi , Fumihito Tomaru
发明人： Hirotake Wakai , Makoto Ohnishi , Fumihito Tomaru
IPC分类号： H04L27/00 , H03D3/00 , H03H17/06 , H04L27/38 , H04L27/22
CPC分类号： H04L27/3854 , H03D3/006 , H03H17/06
摘要： A digital demodulator which demodulates an analog signal obtained through a quadrature amplitude modulation to produce a digital demodulated signal includes a converter to convert the analog signal into a digital signal and a signal processor to quadrature-demodulating the digital signal from the converter. Assuming that the analog signal has a carrier frequency of f.sub.IF and the signal conversion is accomplished with the sampling frequency fs, the demodulator is set to satisfy fs=4.multidot.f.sub.IF /(2n+1), where n denotes a positive integer. The signal processing section conducts the quadrature demodulation according to a quadrature local oscillation signal having a frequency fc satisfying fc=fs/4.
摘要翻译：解调通过正交幅度调制获得的模拟信号以产生数字解调信号的数字解调器包括将模拟信号转换为数字信号的转换器和信号处理器以对来自转换器的数字信号进行正交解调。假设模拟信号具有fIF的载波频率并以采样频率fs完成信号转换，则解调器被设置为满足fs = 4xfIF /（2n + 1），其中n表示正整数。信号处理部根据具有满足fc = fs / 4的频率fc的正交本地振荡信号进行正交解调。

9. 发明授权

US4680556A Digital modulation apparatus 失效
标题翻译：数字调制装置
公开(公告)号：US4680556A
公开(公告)日：1987-07-14
申请号：US850097
申请日：1986-04-10
申请人： Shigeki Nakamura , Makoto Ohnishi , Yasufumi Takahashi
发明人： Shigeki Nakamura , Makoto Ohnishi , Yasufumi Takahashi
IPC分类号： H04L27/20 , H03C3/00
CPC分类号： H04L27/2092
摘要： A quadrature phase modulator constructed by use of a simple digital circuit. Digital signals of sample data obtained by sampling outputs from a roll-off filter with a frequency four times a modulated carrier frequency are stored in an ROM, the outputs corresponding to all combinations of a plurality of successive bits of input data; the plurality of bits are set as an address, and a signal of an in-phase channel and a signal of a quadrature phase channel is alternately read from the ROM with a frequency equal to half the sampling frequency, then the obtained serial signals are subjected to a digital-to-analog conversion to obtain a quadrature phase modulated signal.
摘要翻译：使用简单数字电路构成的正交相位调制器。通过对来自具有调制载波频率的四倍的滚降滤波器的输出的输出获得的采样数据的数字信号存储在ROM中，该输出对应于输入数据的多个连续位的所有组合; 将多个位设置为地址，并且以等于采样频率的一半的频率从ROM交替地读取同相信道的信号和正交相位信号的信号，然后获得的串行信号被进行数模转换以获得正交相位调制信号。

10. 发明授权

US4223389A Recursive digital filter having means to prevent overflow oscillation 失效
标题翻译：递归数字滤波器具有防止溢出振荡的装置
公开(公告)号：US4223389A
公开(公告)日：1980-09-16
申请号：US909066
申请日：1978-05-24
申请人： Eiichi Amada , Makoto Ohnishi
发明人： Eiichi Amada , Makoto Ohnishi
IPC分类号： E04G1/22 , H03H17/04 , G06F15/34 , G06F7/38
CPC分类号： H03H17/0461 , H03H17/0405
摘要： This invention has been made in order to prevent the malfunction due to an overflow, of a combinatorial type recursive digital filter whose feedback side is of the second or higher order. Means for detecting the overflow of the output of an arithmetic unit which executes an addition within the filter is additionally provided, and when the overflow has developed, the contents of shift registers for delay on, at least, the feedback side are reset by an output from the detecting means.
摘要翻译：本发明是为了防止由于溢出而引起的反馈侧为二阶以上的组合型递归数字滤波器的故障。附加地提供用于检测在滤波器内执行相加的运算单元的输出的溢出的装置，并且当溢出发展时，至少在反馈侧的延迟的移位寄存器的内容被输出从检测装置。

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