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1. 发明申请

US20100060254A1 DC-DC converter 有权
标题翻译： DC-DC转换器
公开(公告)号：US20100060254A1
公开(公告)日：2010-03-11
申请号：US12585123
申请日：2009-09-03
申请人： Norihito Tokura , Hisato Kato , Norikazu Kanatake , Masakiyo Horie
发明人： Norihito Tokura , Hisato Kato , Norikazu Kanatake , Masakiyo Horie
IPC分类号： G05F5/00
CPC分类号： H02M3/158
摘要： A synchronous-rectifier type DC-DC converter includes a high-side main switch element, a low-side rectifying switch element, and a control drive circuit. The rectifying switch element includes a rectifying transistor element and a rectifying diode element connected in antiparallel with the rectifying transistor element. The control drive circuit detects an input voltage to the main switch element and determines the input voltage or a rate of increase in the input voltage. When the determined value exceeds a predetermined reference value, a complementary ON/OFF operation of the main switch element and the rectifying transistor element is released, and a state where both the main switch element and the rectifying transistor element are kept OFF for a time period that is longer than a dead-time during the complementary ON/OFF operation is set.
摘要翻译：同步整流型DC-DC转换器包括高侧主开关元件，低侧整流开关元件和控制驱动电路。整流开关元件包括整流晶体管元件和与整流晶体管元件反并联连接的整流二极管元件。控制驱动电路检测到主开关元件的输入电压，并确定输入电压或输入电压的增加率。当确定的值超过预定的参考值时，主开关元件和整流晶体管元件的互补的导通/截止操作被解除，并且主开关元件和整流晶体管元件两者保持断开一段时间的状态在补充ON / OFF操作期间比死区时间长。

2. 发明授权

US08179106B2 DC-DC converter 有权
标题翻译： DC-DC转换器
公开(公告)号：US08179106B2
公开(公告)日：2012-05-15
申请号：US12585123
申请日：2009-09-03
申请人： Norihito Tokura , Hisato Kato , Norikazu Kanatake , Masakiyo Horie
发明人： Norihito Tokura , Hisato Kato , Norikazu Kanatake , Masakiyo Horie
IPC分类号： G05F1/613
CPC分类号： H02M3/158
摘要： A synchronous-rectifier type DC-DC converter includes a high-side main switch element, a low-side rectifying switch element, and a control drive circuit. The rectifying switch element includes a rectifying transistor element and a rectifying diode element connected in antiparallel with the rectifying transistor element. The control drive circuit detects an input voltage to the main switch element and determines the input voltage or a rate of increase in the input voltage. When the determined value exceeds a predetermined reference value, a complementary ON/OFF operation of the main switch element and the rectifying transistor element is released, and a state where both the main switch element and the rectifying transistor element are kept OFF for a time period that is longer than a dead-time during the complementary ON/OFF operation is set.
摘要翻译：同步整流型DC-DC转换器包括高侧主开关元件，低侧整流开关元件和控制驱动电路。整流开关元件包括整流晶体管元件和与整流晶体管元件反并联连接的整流二极管元件。控制驱动电路检测到主开关元件的输入电压，并确定输入电压或输入电压的增加率。当确定的值超过预定的参考值时，主开关元件和整流晶体管元件的互补的导通/截止操作被解除，并且主开关元件和整流晶体管元件两者保持断开一段时间的状态在补充ON / OFF操作期间比死区时间长。

3. 发明申请

US20120032313A1 SEMICONDUCTOR DEVICE HAVING LATERAL DIODE 有权
标题翻译：具有横向二极管的半导体器件
公开(公告)号：US20120032313A1
公开(公告)日：2012-02-09
申请号：US13197719
申请日：2011-08-03
申请人： Takao YAMAMOTO , Norihito Tokura , Hisato Kato , Akio Nakagawa
发明人： Takao YAMAMOTO , Norihito Tokura , Hisato Kato , Akio Nakagawa
IPC分类号： H01L29/861
CPC分类号： H01L29/868 , H01L27/0664 , H01L29/0615 , H01L29/0692 , H01L29/0878 , H01L29/1095 , H01L29/405 , H01L29/42368 , H01L29/7394 , H01L29/7824
摘要： A semiconductor device having a lateral diode includes a semiconductor layer, a first semiconductor region in the semiconductor layer, a contact region having an impurity concentration greater than that of the first semiconductor region, a second semiconductor region located in the semiconductor layer and separated from the contact region, a first electrode electrically connected through the contact region to the first semiconductor region, and a second electrode electrically connected to the second semiconductor region. The second semiconductor region includes a low impurity concentration portion, a high impurity concentration portion, and an extension portion. The second electrode forms an ohmic contact with the high impurity concentration portion. The extension portion has an impurity concentration greater than that of the low impurity concentration portion and extends in a thickness direction of the semiconductor layer.
摘要翻译：具有横向二极管的半导体器件包括半导体层，半导体层中的第一半导体区域，具有大于第一半导体区域的杂质浓度的杂质浓度的接触区域，位于半导体层中并与该半导体层分离的第二半导体区域接触区域，通过接触区域电连接到第一半导体区域的第一电极和与第二半导体区域电连接的第二电极。第二半导体区域包括低杂质浓度部分，高杂质浓度部分和延伸部分。第二电极与高杂质浓度部分形成欧姆接触。延伸部分的杂质浓度大于低杂质浓度部分的杂质浓度，并且在半导体层的厚度方向上延伸。

4. 发明申请

US20090001411A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20090001411A1
公开(公告)日：2009-01-01
申请号：US12155949
申请日：2008-06-12
申请人： Norihito Tokura , Hiroki Sone , Shinji Amano , Hisato Kato
发明人： Norihito Tokura , Hiroki Sone , Shinji Amano , Hisato Kato
IPC分类号： H01L29/739
CPC分类号： H01L27/0664 , H01L29/407 , H01L29/7391 , H01L29/7397 , H01L29/861
摘要： A semiconductor device includes a spaced-channel IGBT and an antiparalell diode that are formed in a same semiconductor substrate. The IGBT includes a base layer and insulated gate trenches by which the base layer is divided into a body region connected to an emitter and a floating region disconnected from the emitter. The IGBT is formed in a cell region of an IGBT region, and the diode is formed in a diode region. A boundary region of the IGBT region is located between the cell region and the diode region. A spacing between adjacent gate trenches in the boundary region is less than a spacing between adjacent gate trenches between which the floating region is located in the cell region.
摘要翻译：半导体器件包括形成在同一半导体衬底中的间隔沟道IGBT和反分解二极管。 IGBT包括基极层和绝缘栅极沟槽，基极层被分成连接到发射极的体区和与发射极断开的浮动区域。 IGBT形成在IGBT区域的单元区域中，二极管形成在二极管区域中。 IGBT区域的边界区域位于单元区域和二极管区域之间。边界区域中的相邻栅极沟槽之间的间隔小于相邻栅极沟槽之间的间隔，在该沟槽之间的浮动区域位于单元区域中。

5. 发明授权

US07616859B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07616859B2
公开(公告)日：2009-11-10
申请号：US12155949
申请日：2008-06-12
申请人： Norihito Tokura , Hiroki Sone , Shinji Amano , Hisato Kato
发明人： Norihito Tokura , Hiroki Sone , Shinji Amano , Hisato Kato
IPC分类号： G02B6/00
CPC分类号： H01L27/0664 , H01L29/407 , H01L29/7391 , H01L29/7397 , H01L29/861
摘要： A semiconductor device includes a spaced-channel IGBT and an antiparallel diode that are formed in a same semiconductor substrate. The IGBT includes a base layer and insulated gate trenches by which the base layer is divided into a body region connected to an emitter and a floating region disconnected from the emitter. The IGBT is formed in a cell region of an IGBT region, and the diode is formed in a diode region. A boundary region of the IGBT region is located between the cell region and the diode region. A spacing between adjacent gate trenches in the boundary region is less than a spacing between adjacent gate trenches between which the floating region is located in the cell region.
摘要翻译：半导体器件包括形成在同一半导体衬底中的间隔沟道IGBT和反并联二极管。 IGBT包括基极层和绝缘栅极沟槽，基极层被分成与发射极连接的主体区域和与发射极断开的浮动区域。 IGBT形成在IGBT区域的单元区域中，二极管形成在二极管区域中。 IGBT区域的边界区域位于单元区域和二极管区域之间。边界区域中的相邻栅极沟槽之间的间隔小于相邻栅极沟槽之间的间隔，在该沟槽之间的浮动区域位于单元区域中。

6. 发明授权

US08742534B2 Semiconductor device having lateral diode 有权
标题翻译：具有侧向二极管的半导体器件
公开(公告)号：US08742534B2
公开(公告)日：2014-06-03
申请号：US13197719
申请日：2011-08-03
申请人： Takao Yamamoto , Norihito Tokura , Hisato Kato , Akio Nakagawa
发明人： Takao Yamamoto , Norihito Tokura , Hisato Kato , Akio Nakagawa
IPC分类号： H01L29/66 , H01L29/47
CPC分类号： H01L29/868 , H01L27/0664 , H01L29/0615 , H01L29/0692 , H01L29/0878 , H01L29/1095 , H01L29/405 , H01L29/42368 , H01L29/7394 , H01L29/7824
摘要： A semiconductor device having a lateral diode includes a semiconductor layer, a first semiconductor region in the semiconductor layer, a contact region having an impurity concentration greater than that of the first semiconductor region, a second semiconductor region located in the semiconductor layer and separated from the contact region, a first electrode electrically connected through the contact region to the first semiconductor region, and a second electrode electrically connected to the second semiconductor region. The second semiconductor region includes a low impurity concentration portion, a high impurity concentration portion, and an extension portion. The second electrode forms an ohmic contact with the high impurity concentration portion. The extension portion has an impurity concentration greater than that of the low impurity concentration portion and extends in a thickness direction of the semiconductor layer.
摘要翻译：具有横向二极管的半导体器件包括半导体层，半导体层中的第一半导体区域，具有大于第一半导体区域的杂质浓度的杂质浓度的接触区域，位于半导体层中并与该半导体层分离的第二半导体区域接触区域，通过接触区域电连接到第一半导体区域的第一电极和与第二半导体区域电连接的第二电极。第二半导体区域包括低杂质浓度部分，高杂质浓度部分和延伸部分。第二电极与高杂质浓度部分形成欧姆接触。延伸部分的杂质浓度大于低杂质浓度部分的杂质浓度，并且在半导体层的厚度方向上延伸。

7. 发明授权

US07586151B2 Insulated gate semiconductor device 有权
标题翻译：绝缘栅半导体器件
公开(公告)号：US07586151B2
公开(公告)日：2009-09-08
申请号：US11578949
申请日：2005-05-11
申请人： Hidefumi Takaya , Yasushi Okura , Akira Kuroyanagi , Norihito Tokura
发明人： Hidefumi Takaya , Yasushi Okura , Akira Kuroyanagi , Norihito Tokura
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0623 , H01L29/0653 , H01L29/42368 , H01L29/4238 , H01L29/7811
摘要： The present invention provides an insulated gate semiconductor device which has floating regions around the bottoms of trenches and which is capable of reliably achieving a high withstand voltage. An insulated gate semiconductor device 100 includes a cell area through which current flows and an terminal area which surrounds the cell area. The semiconductor device 100 also has a plurality of gate trenches 21 in the cell area and a plurality of terminal trenches 62 in the terminal area. The gate trenches 21 are formed in a striped shape, and the terminal trenches 62 are formed concentrically. In the semiconductor device 100, the gate trenches 21 and the terminal trenches 62 are positioned in a manner that spacings between the ends of the gate trenches 21 and the side of the terminal trench 62 are uniform. That is, the length of the gate trenches 21 is adjusted according to the curvature of the corners of the terminal trench 62.
摘要翻译：本发明提供了一种绝缘栅半导体器件，其在沟槽底部附近具有浮动区域，并且能够可靠地实现高耐压。绝缘栅半导体器件100包括电流流过的单元区域和围绕单元区域的端子区域。半导体器件100还在单元区域中具有多个栅极沟槽21以及端子区域中的多个端子沟槽62。栅极沟槽21形成为条状，并且端子沟槽62同心地形成。在半导体器件100中，栅极沟槽21和端子沟槽62以栅极沟槽21的端部和端子沟槽62的侧面之间的间隔均匀的方式定位。也就是说，栅极沟槽21的长度根据端子沟槽62的拐角的曲率来调节。

8. 发明申请

US20070200138A1 Semiconductor device having IGBT and diode 有权
标题翻译：具有IGBT和二极管的半导体器件
公开(公告)号：US20070200138A1
公开(公告)日：2007-08-30
申请号：US11709272
申请日：2007-02-22
申请人： Yoshihiko Ozeki , Norihito Tokura , Yukio Tsuzuki
发明人： Yoshihiko Ozeki , Norihito Tokura , Yukio Tsuzuki
IPC分类号： H01L29/74
CPC分类号： H01L27/0611 , H01L29/7395 , H01L29/8611
摘要： A semiconductor device includes: a semiconductor substrate; a IGBT region including a first region on a first surface of the substrate and providing a channel-forming region and a second region on a second surface of the substrate and providing a collector; a diode region including a third region on the first surface and providing an anode or a cathode and a fourth region on the second surface and providing the anode or the cathode; a periphery region including a fifth region on the first surface and a sixth region on the second surface. The first, third and fifth regions are commonly and electrically coupled, and the second, fourth and sixth regions are commonly and electrically coupled with one another.
摘要翻译：半导体器件包括：半导体衬底; IGBT区域，包括在所述基板的第一表面上的第一区域，并且在所述基板的第二表面上提供沟道形成区域和第二区域，并提供集电体; 二极管区域，包括在第一表面上的第三区域，并在第二表面上提供阳极或阴极和第四区域，并提供阳极或阴极; 外围区域，包括在第一表面上的第五区域和第二表面上的第六区域。第一，第三和第五区域通常和电耦合，并且第二，第四和第六区域彼此通常电耦合。

9. 发明授权

US6133587A Silicon carbide semiconductor device and process for manufacturing same 失效
标题翻译：碳化硅半导体器件及其制造方法
公开(公告)号：US6133587A
公开(公告)日：2000-10-17
申请号：US23280
申请日：1998-02-13
申请人： Yuichi Takeuchi , Takeshi Miyajima , Norihito Tokura , Hiroo Fuma , Toshio Murata , Takamasa Suzuki , Shoichi Onda
发明人： Yuichi Takeuchi , Takeshi Miyajima , Norihito Tokura , Hiroo Fuma , Toshio Murata , Takamasa Suzuki , Shoichi Onda
IPC分类号： H01L21/04 , H01L29/06 , H01L29/24 , H01L29/78 , H01L31/0312
CPC分类号： H01L29/7813 , H01L29/1608 , H01L29/66068 , H01L29/7838 , H01L29/0696
摘要： A n.sup.- -type source region 5 is formed on a predetermined region of the surface layer section of the p-type silicon carbide semiconductor layer 3 of a semiconductor substrate 4. A low-resistance p-type silicon carbide region 6 is formed on a predetermined region of the surface layer section in the p-type silicon carbide semiconductor layer 3. A trench 7 is formed in a predetermined region in the n.sup.+ -type source region 5, which trench 7 passes through the n.sup.+ -type source region 5 and the p-type silicon carbide semiconductor layer 3, reaching the n.sup.- -type silicon carbide semiconductor layer 2. The trench 7 has side walls 7a perpendicular to the surface of the semiconductor substrate 4 and a bottom side 7b parallel to the surface of the semiconductor substrate 4. The hexagonal region surrounded by the side walls 7a of the trench 7 is an island semiconductor region 12. A high-reliability gate insulating film 8 is obtained by forming a gate insulating layer on the side walls 7a which surround the island semiconductor region 12.
摘要翻译： n型源极区5形成在半导体衬底4的p型碳化硅半导体层3的表层部分的预定区域上。低电阻p型碳化硅区6形成在在p型碳化硅半导体层3中的表层部分的预定区域。沟槽7形成在n +型源极区域5中的预定区域中，沟槽7通过n +型源极区域5，并且 p型碳化硅半导体层3，到达n型碳化硅半导体层2.沟槽7具有垂直于半导体衬底4的表面的侧壁7a和平行于半导体衬底的表面的底侧7b 由沟槽7的侧壁7a包围的六边形区域是岛状半导体区域12.通过在侧壁7a上形成栅极绝缘层，形成高可靠性栅极绝缘膜8，岛半导体区域12。

10. 发明授权

US6133120A Boron-doped p-type single crystal silicon carbide semiconductor and process for preparing same 失效
标题翻译：硼掺杂的p型单晶碳化硅半导体及其制备方法
公开(公告)号：US6133120A
公开(公告)日：2000-10-17
申请号：US704820
申请日：1996-08-28
申请人： Takeshi Miyajima , Norihito Tokura , Atsuo Fukumoto , Hidemitsu Hayashi
发明人： Takeshi Miyajima , Norihito Tokura , Atsuo Fukumoto , Hidemitsu Hayashi
IPC分类号： H01L21/205 , C30B25/00 , C30B25/02 , H01L21/04 , H01L21/20 , H01L21/265 , H01L21/336 , H01L29/12 , H01L29/24 , H01L29/78 , C01B31/36
CPC分类号： H01L29/7813 , C30B25/00 , C30B25/02 , C30B29/36 , H01L21/0455 , H01L29/66068 , H01L29/1608 , Y10S438/931
摘要： A p-type silicon carbide semiconductor having a high carrier concentration and activation rate is provided by doping boron as an acceptor impurity in a single crystal silicon carbide. The boron occupies silicon sites in a crystal lattice of the single crystal silicon carbide.
摘要翻译：通过在单晶碳化硅中掺杂硼作为受主杂质来提供具有高载流子浓度和活化速率的p型碳化硅半导体。硼占据单晶碳化硅的晶格中的硅位置。

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