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    • 2. 发明授权
    • Field-effect transistor and method of producing same
    • 场效应晶体管及其制造方法
    • US5640029A
    • 1997-06-17
    • US551285
    • 1995-10-31
    • Toyokazu Ohnishi
    • Toyokazu Ohnishi
    • H01L29/872H01L21/265H01L21/28H01L21/285H01L21/338H01L29/08H01L29/423H01L29/47H01L29/812H01L29/80H01L21/26
    • H01L29/66878H01L21/2815H01L21/28587H01L29/0891H01L29/42316
    • A field-effect transistor has its gate length made to be minute, and a short channel effect is prevented. The field-effect transistor which attains the above objects has first and second semiconductor regions having different impurity concentrations disposed so as to be adjacent to each other. A source electrode is disposed on the second semiconductor region with a high impurity concentration, a drain electrode on the first semiconductor region with a low impurity concentration, and a gate electrode on the first semiconductor region side of the second semiconductor region. To produce the above field-effect transistor, a production method comprises a step of forming a first semiconductor region on the major surface of a semiconductor substrate, a step of forming a gate electrode to divide the first semiconductor region, and a step of doping impurities in the first semiconductor region on one side of the gate electrode with the gate electrode as the mask, to form a second semiconductor region which is of the same conductive type with the first semiconductor region and has a different impurity concentration from the first semiconductor region.
    • 场效应晶体管的栅极长度使其微小,并且防止短沟道效应。 实现上述目的的场效应晶体管具有彼此相邻配置的具有不同杂质浓度的第一和第二半导体区域。 源电极设置在具有高杂质浓度的第二半导体区域上,具有低杂质浓度的第一半导体区上的漏电极和在第二半导体区域的第一半导体区域侧上的栅电极。 为了制造上述场效应晶体管,制造方法包括在半导体基板的主表面上形成第一半导体区域的步骤,形成用于分割第一半导体区域的栅电极的工序,以及掺杂杂质的工序 在栅电极的一侧的第一半导体区域中,以栅电极为掩模,与第一半导体区域形成与第一半导体区域具有相同导电类型且与第一半导体区域具有不同杂质浓度的第二半导体区域。
    • 3. 发明授权
    • MOSFET having Schottky gate and bipolar device
    • 具有肖特基栅极和双极器件的MOSFET
    • US5994725A
    • 1999-11-30
    • US003438
    • 1998-01-06
    • Toyokazu OhnishiAkinori Seki
    • Toyokazu OhnishiAkinori Seki
    • H01J9/02H01L21/338H01L29/423H01L29/812H01L29/73
    • H01L29/66856H01J9/025H01L29/42316H01L29/66863H01L29/8124H01L29/8128
    • A semiconductor device having a Schottky gate and a bipolar device. A semiconductor substrate has a surface layer in ohmic contact with the conductor and the deeper layer in Schottky contact with the conductor. The substrate has a recess which reaches into the deeper layer. A conductor field extends from the bottom of the recess in a direction perpendicular to the bottom. Insulating films are formed on both vertical surfaces of the conductor film. Another conductor film is formed across the top of the first conductor film and both insulating films. Conductor films are formed on the surface of the substrate on either side of the insulating films. In this device, the electrode length/width is reduced and the response to the element is improved. Further, because the second conductor film is formed on the first conductor film, it is possible to reduce the gate electrode and the base electrode.
    • 具有肖特基栅极和双极器件的半导体器件。 半导体衬底具有与导体欧姆接触的表面层和与导体肖特基接触的较深层。 衬底具有进入更深层的凹陷。 导体场从垂直于底部的方向从凹部的底部延伸。 绝缘膜形成在导体膜的两个垂直表面上。 在第一导体膜的顶部和两个绝缘膜上形成另一个导体膜。 在绝缘膜两侧的基板表面上形成导体膜。 在该器件中,电极长度/宽度减小,并且对元件的响应得到改善。 此外,由于第二导体膜形成在第一导体膜上,所以可以减小栅电极和基极。
    • 5. 发明申请
    • SEMICONDUCTOR DEVICE
    • 半导体器件
    • US20100289076A1
    • 2010-11-18
    • US12808473
    • 2008-11-11
    • Shuichi NishidaToyokazu OhnishiTomoyuki Shoji
    • Shuichi NishidaToyokazu OhnishiTomoyuki Shoji
    • H01L29/78
    • H01L29/7813H01L29/0649H01L29/0653H01L29/0696H01L29/0834H01L29/407H01L29/7397
    • A technique is presented for further reducing on-resistance (or on-voltage) in a vertical semiconductor device provided with a carrier shielding layer.A semiconductor substrate 20 of a semiconductor device 10 comprises a channel section 10A and a non-channel section 10B. An emitter region 26 is formed in the channel section 10A, this emitter region 26 making contact with a side surface of a trench gate 30 and being electrically connected to an emitter electrode 28. The emitter region 26 is not formed in a body region 25 of the non-channel section 10B. In a plan view, an occupied area ratio of the area which a carrier shielding layer 52 located in the non-channel section 10B occupies within the non-channel section 10B is larger than an occupied area ratio of the area which the carrier shielding layer 52 located in the channel section 10A occupies within the channel section 10A.
    • 提出了一种技术,用于在具有载体屏蔽层的垂直半导体器件中进一步降低导通电阻(或导通电压)。 半导体器件10的半导体衬底20包括沟道部分10A和非沟道部分10B。 发射极区域26形成在沟道部分10A中,该发射极区域26与沟槽栅极30的侧表面接触并且电连接到发射极电极28.发射极区域26不形成在 非通道部分10B。 在平面图中,位于非通道部10B中的载流子屏蔽层52所占据的区域的占用面积比大于非沟道部分10B中的载流子屏蔽层52所占的面积比 位于通道部分10A中的通道部分10A占据通道部分10A。
    • 6. 发明授权
    • Method of manufacturing a semiconductor device
    • 制造半导体器件的方法
    • US5773334A
    • 1998-06-30
    • US531606
    • 1995-09-21
    • Toyokazu OhnishiAkinori Seki
    • Toyokazu OhnishiAkinori Seki
    • H01J9/02H01L21/338H01L29/423H01L29/812H01L21/283H01L21/331
    • H01L29/66856H01J9/025H01L29/42316H01L29/66863H01L29/8124H01L29/8128
    • A semiconductor device is manufactured by a process comprising the steps of forming a cover film on a surface of a semiconductor substrate such that the cover film exposes a portion of the surface, covers a remaining portion thereof and has an edge along a boundary between the exposed portion and the covered portion, forming a first conductor film in a range from the cover film formed in the cover film forming step through the edge to the exposed surface portion of the semiconductor substrate, removing the first conductor film formed in the first conductor film forming step other than a portion formed along the edge such that the first conductor film is left along the edge, forming an insulating film on the opposite sides of the first conductor film left along the edge in the removing step such that a top edge of the left first conductor film is exposed, and forming a second conductor film on the surface of the insulating film formed in the insulating film forming step along the exposed top edge of the first conductor film. In this method, the gate electrode or the base electrode is formed by a side wall process. It is thus possible to reduce the electrode length/width and improve the response of the element.
    • 半导体器件通过以下工艺制造,该方法包括以下步骤:在半导体衬底的表面上形成覆盖膜,使得覆盖膜暴露表面的一部分,覆盖其剩余部分,并且沿着暴露的 在覆盖膜形成步骤中形成的覆盖膜通过边缘到半导体衬底的暴露表面部分的范围内形成第一导体膜,去除形成在第一导体膜形成中的第一导体膜 除了沿着边缘形成的部分之外,使得第一导体膜沿着边缘留下,在除去步骤中沿着边缘留下的第一导体膜的相对侧上形成绝缘膜,使得左边的顶部边缘 暴露第一导体膜,并且在沿着曝光的绝缘膜形成步骤中形成的绝缘膜的表面上形成第二导体膜 d第一导体膜的顶部边缘。 在该方法中,通过侧壁工艺形成栅电极或基极。 因此可以减小电极的长度/宽度并改善元件的响应。