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1. 发明授权

US06938248B2 Program preparation apparatus 失效
标题翻译：程序准备装置
公开(公告)号：US06938248B2
公开(公告)日：2005-08-30
申请号：US09971683
申请日：2001-10-09
申请人： Naoichi Kitakami , Akiya Fukui , Kazuya Takahashi
发明人： Naoichi Kitakami , Akiya Fukui , Kazuya Takahashi
IPC分类号： G06F9/45
CPC分类号： G06F8/4432 , Y02D10/41
摘要： A program preparation apparatus that can reduce power consumption and that can suppress malfunctions and the occurrence of noise by improving software is provided. An assembler prepares a relative object program based on an assembly source program. Next, the assembler changes the order of instructions included in the assembly source program in a range that does not influence the operational results in a CPU and, thereby, prepares another assembly source program so as to prepare a relative object program based on this assembly source program. Next, the assembler finds the respective maximum Hamming distance values between respective instructions for a plurality of relative object programs so that the program of which the maximum Hamming distance value is the lowest is determined as a formal relative object program.
摘要翻译：提供了一种可以通过改进软件来降低功耗并且可以抑制故障和产生噪声的程序制备装置。汇编程序基于汇编源程序准备相对对象程序。接下来，汇编器将包含在汇编源程序中的指令的顺序改变在不影响CPU中的运算结果的范围内，从而准备另一个汇编源程序，以便根据该汇编源准备相对对象程序程序。接下来，汇编器找到多个相对对象程序的相应指令之间的相应最大汉明距离值，使得最大汉明距离值最低的程序被确定为正式的相对对象程序。

2. 发明授权

US5031097A Direct memory access controller 失效
标题翻译：直接内存访问控制器
公开(公告)号：US5031097A
公开(公告)日：1991-07-09
申请号：US398815
申请日：1989-08-25
申请人： Naoichi Kitakami , Yuichi Nakao , Hiroyuki Kondo , Hideharu Toyomoto , Koji Tsuchihashi
发明人： Naoichi Kitakami , Yuichi Nakao , Hiroyuki Kondo , Hideharu Toyomoto , Koji Tsuchihashi
IPC分类号： G06F13/28 , G06F13/30
CPC分类号： G06F13/30
摘要： A direct memory access controller has a data assembly function by means of a single temporary register. This single register used for a number of channels replaces temporary registers which have been necessary for the respective channels to carry out channel transition during data assembly. By controlling channel transition during data assembly, it is possible to carry out DMA transfers in which channel transition is made during data assembly, thereby preventing an increase in the chip size.
摘要翻译：直接存储器访问控制器通过单个临时寄存器具有数据组合功能。用于多个通道的单个寄存器替代了在数据组合期间各个通道执行通道转换所必需的临时寄存器。通过在数据组合期间控制信道转换，可以执行在数据组合期间进行信道转换的DMA传输，从而防止芯片尺寸的增加。

3. 发明授权

US06928499B2 Microcomputer used in system having external storing unit and/or peripheral unit 失效
标题翻译：在具有外部存储单元和/或外围单元的系统中使用的微型计算机
公开(公告)号：US06928499B2
公开(公告)日：2005-08-09
申请号：US10138493
申请日：2002-05-06
申请人： Naoichi Kitakami
发明人： Naoichi Kitakami
IPC分类号： G06F3/00 , G06F13/16 , G06F13/42 , G06F15/78 , G06F13/00
CPC分类号： G06F13/4213 , G06F13/1668
摘要： An external area judging unit judges according to an address signal of a CPU whether the access to an external memory or the access to a peripheral unit is desired. In cases where the access to the external memory (or the peripheral unit) is desired, a bus selection signal indicating the external memory (or the peripheral unit) is sent to a bus control unit, and a plurality of bus control signals received in the bus control unit from the CPU are sent to the external memory (or the peripheral unit) as a plurality of external bus signals based on a bus timing for the external memory (or the peripheral unit) to make the CPU gain access to the external memory (or the peripheral unit).
摘要翻译：外部区域判断单元根据CPU的地址信号判断是否需要对外部存储器的访问或对外围单元的访问。在需要访问外部存储器（或外围单元）的情况下，将指示外部存储器（或外围单元）的总线选择信号发送到总线控制单元，并且在该控制单元中接收多个总线控制信号基于外部存储器（或外围单元）的总线定时，来自CPU的总线控制单元作为多个外部总线信号被发送到外部存储器（或外围单元），以使CPU获得对外部存储器的访问（或外围设备）。

4. 发明授权

US6070216A Serial I/O multichannel semiconductor device capable of selecting a transmitting pin for data output and of detecting received data at a plurality of receiving pins 失效
标题翻译：串行I / O多通道半导体器件，其能够选择用于数据输出的发送引脚和检测多个接收引脚处的接收数据
公开(公告)号：US6070216A
公开(公告)日：2000-05-30
申请号：US92071
申请日：1998-06-05
申请人： Naoichi Kitakami , Hiroki Takahashi
发明人： Naoichi Kitakami , Hiroki Takahashi
IPC分类号： G06F15/78 , G06F1/22 , G06F13/38 , H04L25/02 , H04L29/04 , G06F3/00 , G06F9/00 , G06F13/00 , G06F13/14
CPC分类号： G06F1/22
摘要： A serial I/O incorporated semiconductor device comprises a transmitting unit 4 including a transmission channel selection register 14 for selecting a transmitting pin to output transmit data and a receiving unit 5 including a receiving channel detection circuit 26 for detecting receiving pins that have received data; a receiving channel flag 27 set to have a predetermined value by the receiving channel detection circuit; a plural channels reception detection circuit 28 for detecting that received data is entered to a plurality of receiving pins; and a plural channels receiving flag 29 set to have a predetermined value by the plural channels reception detection circuit 28 detecting received data has been entered to the plurality of receiving pins; wherein when any one of the flags 23, 25, and 29 is set to a predetermined value, the receiving unit supplies the value to a CPU as a reception interrupt signal.
摘要翻译：串行I / O并入的半导体器件包括：发送单元4，包括用于选择发送引脚以输出发送数据的发送信道选择寄存器14;以及接收单元5，包括：接收信道检测电路26，用于检测接收到的数据的接收引脚; 由接收信道检测电路设置为具有预定值的接收信道标志27; 用于检测接收的数据被输入到多个接收引脚的多频道接收检测电路28; 并且多个信道接收标志29被多个信道接收检测电路28检测接收到的数据设置为具有预定值已被输入到多个接收引脚; 其中当标志23,25和29中的任何一个被设置为预定值时，接收单元将该值作为接收中断信号提供给CPU。

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