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1. 发明公开

US20230409486A1 FAULT BUFFER FOR TRACKING PAGE FAULTS IN UNIFIED VIRTUAL MEMORY SYSTEM 审中-公开
公开(公告)号：US20230409486A1
公开(公告)日：2023-12-21
申请号：US18456420
申请日：2023-08-25
申请人： NVIDIA CORPORATION
发明人： Jerome F. DULUK, Jr. , Cameron BUSCHARDT , Sherry CHEUNG , James Leroy DEMING , Samuel H. DUNCAN , Lucien DUNNING , Robert GEORGE , Arvind GOPALAKRISHNAN , Mark HAIRGROVE , Chenghuan JIA , John MASHEY
IPC分类号： G06F12/1009 , G06F11/07 , G06F12/08 , G06F12/1072 , G06F12/109 , G06F12/12
CPC分类号： G06F12/1009 , G06F11/073 , G06F11/0793 , G06F12/08 , G06F12/1072 , G06F12/109 , G06F12/12 , G06F12/10
摘要： A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.

2. 发明申请

US20140281297A1 MIGRATION OF PEER-MAPPED MEMORY PAGES 有权
标题翻译：对等记录页的移植
公开(公告)号：US20140281297A1
公开(公告)日：2014-09-18
申请号：US14134148
申请日：2013-12-19
申请人： NVIDIA CORPORATION
发明人： Jerome F. DULUK, JR. , John MASHEY , Mark HAIRGROVE , Chenghuan JIA , Cameron BUSCHARDT , Lucien DUNNING , Brian FAHS
IPC分类号： G06F12/10 , G06F12/12
CPC分类号： G06F3/0604 , G06F3/0647 , G06F3/0664 , G06F12/0804 , G06F12/1009 , G06F13/4022 , G06F13/4282 , G06F2212/657
摘要： Techniques are provided by which memory pages may be migrated among PPU memories in a multi-PPU system. According to the techniques, a UVM driver determines that a particular memory page should change ownership state and/or be migrated between one PPU memory and another PPU memory. In response to this determination, the UVM driver initiates a peer transition sequence to cause the ownership state and/or location of the memory page to change. Various peer transition sequences involve modifying mappings for one or more PPU, and copying a memory page from one PPU memory to another PPU memory. Several steps in peer transition sequences may be performed in parallel for increased processing speed.
摘要翻译：提供了技术，通过该技术可以在多PPU系统中的PPU存储器之间迁移存储器页面。根据这些技术，UVM驱动程序确定特定存储器页面应该改变所有权状态和/或在一个PPU存储器和另一个PPU存储器之间迁移。响应于该确定，UVM驱动程序启动对等体转换序列以使存储器页的所有权状态和/或位置改变。各种对等体转换序列涉及修改一个或多个PPU的映射，以及将存储器页面从一个PPU存储器复制到另一个PPU存储器。可以并行执行对等转换序列中的几个步骤，以提高处理速度。

3. 发明申请

US20140281263A1 REPLAYING MEMORY TRANSACTIONS WHILE RESOLVING MEMORY ACCESS FAULTS 有权
标题翻译：在解决存储器访问错误时重新进行内存交易
公开(公告)号：US20140281263A1
公开(公告)日：2014-09-18
申请号：US14109678
申请日：2013-12-17
申请人： NVIDIA CORPORATION
发明人： James Leroy DEMING , Jerome F. DULUK, Jr. , John MASHEY , Mark HAIRGROVE , Lucien DUNNING , Jonathon Stuart Ramsay EVANS , Samuel H. DUNCAN , Cameron BUSCHARDT , Brian FAHS
IPC分类号： G06F12/10 , G06F12/08 , G06F12/12
CPC分类号： G06F12/1027 , G06F9/467 , G06F12/08 , G06F2212/301 , G06F2212/684
摘要： One embodiment of the present invention is a parallel processing unit (PPU) that includes one or more streaming multiprocessors (SMs) and implements a replay unit per SM. Upon detecting a page fault associated with a memory transaction issued by a particular SM, the corresponding replay unit causes the SM, but not any unaffected SMs, to cease issuing new memory transactions. The replay unit then stores the faulting memory transaction and any faulting in-flight memory transaction in a replay buffer. As page faults are resolved, the replay unit replays the memory transactions in the replay buffer—removing successful memory transactions from the replay buffer—until all of the stored memory transactions have successfully executed. Advantageously, the overall performance of the PPU is improved compared to conventional PPUs that, upon detecting a page fault, stop performing memory transactions across all SMs included in the PPU until the fault is resolved.
摘要翻译：本发明的一个实施例是包括一个或多个流式多处理器（SM）并且实现每SM的重放单元的并行处理单元（PPU）。当检测到与由特定SM发出的存储器事务相关联的页面错误时，相应的重放单元使得SM，而不是任何未受影响的SM停止发行新的存储器事务。重播单元然后将故障存储器事务和任何故障的飞行中存储器事务存储在重放缓冲器中。当页面错误得到解决时，重播单元重播重播缓冲区中的内存事务，从重播缓冲区中移除成功的内存事务，直到所有存储的内存事务都已成功执行。有利的是，与常规PPU相比，PPU的整体性能得到改善，在常规PPU检测到页面故障之后，停止执行包含在PPU中的所有SM的存储器事务，直到故障被解决为止。

4. 发明申请

US20140123145A1 EFFICIENT MEMORY VIRTUALIZATION IN MULTI-THREADED PROCESSING UNITS 审中-公开
公开(公告)号：US20140123145A1
公开(公告)日：2014-05-01
申请号：US13660763
申请日：2012-10-25
申请人： NVIDIA CORPORATION
发明人： Nick BARROW-WILLIAMS , Brian FAHS , Jerome F. DULUK, Jr. , James Leroy DEMING , Timothy John PURCELL , Lucien DUNNING , Mark HAIRGROVE
IPC分类号： G06F9/46
CPC分类号： G06F9/5027 , G06F12/1045 , G06F12/109
摘要： A technique for simultaneously executing multiple tasks, each having an independent virtual address space, involves assigning an address space identifier (ASID) to each task and constructing each virtual memory access request to include both a virtual address and the ASID. During virtual to physical address translation, the ASID selects a corresponding page table, which includes virtual to physical address mappings for the ASID and associated task. Entries for a translation look-aside buffer (TLB) include both the virtual address and ASID to complete each mapping to a physical address. Deep scheduling of tasks sharing a virtual address space may be implemented to improve cache affinity for both TLB and data caches.

5. 发明申请

US20140122829A1 EFFICIENT MEMORY VIRTUALIZATION IN MULTI-THREADED PROCESSING UNITS 审中-公开
标题翻译：多线程处理单元的高效内存虚拟化
公开(公告)号：US20140122829A1
公开(公告)日：2014-05-01
申请号：US13660815
申请日：2012-10-25
申请人： NVIDIA CORPORATION
发明人： Nick BARROW-WILLIAMS , Brian FAHS , Jerome F. DULUK, JR. , James Leroy DEMING , Timothy John PURCELL , Lucien DUNNING , Mark HAIRGROVE
IPC分类号： G06F12/10
CPC分类号： G06F12/08 , G06F12/1009 , G06F12/1027 , G06F2212/684
摘要： A technique for simultaneously executing multiple tasks, each having an independent virtual address space, involves assigning an address space identifier (ASID) to each task and constructing each virtual memory access request to include both a virtual address and the ASID. During virtual to physical address translation, the ASID selects a corresponding page table, which includes virtual to physical address mappings for the ASID and associated task. Entries for a translation look-aside buffer (TLB) include both the virtual address and ASID to complete each mapping to a physical address. Deep scheduling of tasks sharing a virtual address space may be implemented to improve cache affinity for both TLB and data caches.
摘要翻译：一种用于同时执行多个任务的技术，每个任务具有独立的虚拟地址空间，包括为每个任务分配地址空间标识符（ASID），并且构建每个虚拟存储器访问请求以包括虚拟地址和ASID。在虚拟到物理地址转换期间，ASID选择相应的页表，其中包括ASID和相关任务的虚拟到物理地址映射。翻译后备缓冲区（TLB）的条目包括虚拟地址和ASID，以完成对物理地址的每个映射。可以实现对共享虚拟地址空间的任务的深度调度，以提高对TLB和数据高速缓存的高速缓存亲和性。

6. 发明申请

US20170329717A9 FAULT BUFFER FOR RESOLVING PAGE FAULTS IN UNIFIED VIRTUAL MEMORY SYSTEM 审中-公开
公开(公告)号：US20170329717A9
公开(公告)日：2017-11-16
申请号：US14055356
申请日：2013-10-16
申请人： NVIDIA CORPORATION
发明人： Jerome F. DULUK, JR. , Cameron BUSCHARDT , Sherry CHEUNG , James Leroy DEMING , Samuel H. DUNCAN , Lucien DUNNING , Robert GEORGE , Arvind GOPALAKRISHNAN , Mark HAIRGROVE , Chenghuan JIA , John MASHEY
IPC分类号： G06F12/1009 , G06F12/08 , G06F12/109 , G06F12/1072 , G06F12/12 , G06F11/07
CPC分类号： G06F12/1009 , G06F11/073 , G06F11/0793 , G06F12/08 , G06F12/10 , G06F12/1072 , G06F12/109 , G06F12/12 , G06F2212/1016
摘要： A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.

7. 发明申请

US20140281296A1 FAULT BUFFER FOR TRACKING PAGE FAULTS IN UNIFIED VIRTUAL MEMORY SYSTEM 审中-公开
标题翻译：用于跟踪统一的虚拟内存系统中的页面故障的故障缓冲区
公开(公告)号：US20140281296A1
公开(公告)日：2014-09-18
申请号：US14055345
申请日：2013-10-16
申请人： NVIDIA Corporation
发明人： Jerome F. DULUK, JR. , Cameron BUSCHARDT , Sherry CHEUNG , James Leroy DEMING , Samuel H. DUNCAN , Lucien DUNNING , Robert GEORGE , Arvind GOPALAKRISHNAN , Mark HAIRGROVE , Chenghuan JIA , John MASHEY
IPC分类号： G06F11/07 , G06F12/12
CPC分类号： G06F12/1009 , G06F11/073 , G06F11/0793 , G06F12/08 , G06F12/10 , G06F12/1072 , G06F12/109 , G06F12/12 , G06F2212/1016
摘要： A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.
摘要翻译：用于管理虚拟内存的系统。该系统包括被配置为执行引用第一虚拟存储器地址的第一操作的第一处理单元。该系统还包括与第一处理单元相关联的第一存储器管理单元（MMU），并且被配置为在确定存储在与第一处理单元相关联的第一存储器单元中的第一页表不包括第一页表时，产生第一页错误对应于第一虚拟存储器地址的映射。该系统还包括与第一处理单元相关联的第一复制引擎。第一复制引擎被配置为读取第一命令队列以确定与第一虚拟存储器地址相对应并且被包括在第一页状态目录中的第一映射。第一复制引擎还被配置为更新第一页表以包括第一映射。

8. 发明申请

US20140281255A1 PAGE STATE DIRECTORY FOR MANAGING UNIFIED VIRTUAL MEMORY 有权
标题翻译：用于管理统一的虚拟内存的页面状态目录
公开(公告)号：US20140281255A1
公开(公告)日：2014-09-18
申请号：US14055318
申请日：2013-10-16
申请人： NVIDIA Corporation
发明人： Jerome F. DULUK, JR. , Cameron BUSCHARDT , Sherry CHEUNG , James Leroy DEMING , Samuel H. DUNCAN , Lucien DUNNING , Robert GEORGE , Arvind GOPALAKRISHNAN , Mark HAIRGROVE , Chenghuan JIA , John MASHEY
IPC分类号： G06F12/10
CPC分类号： G06F12/1009 , G06F11/073 , G06F11/0793 , G06F12/08 , G06F12/10 , G06F12/1072 , G06F12/109 , G06F12/12 , G06F2212/1016
摘要： A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.
摘要翻译：用于管理虚拟内存的系统。该系统包括被配置为执行引用第一虚拟存储器地址的第一操作的第一处理单元。该系统还包括与第一处理单元相关联的第一存储器管理单元（MMU），并且被配置为在确定存储在与第一处理单元相关联的第一存储器单元中的第一页表不包括第一页表时，生成第一页错误对应于第一虚拟存储器地址的映射。该系统还包括与第一处理单元相关联的第一复制引擎。第一复制引擎被配置为读取第一命令队列以确定与第一虚拟存储器地址相对应并且被包括在第一页状态目录中的第一映射。第一复制引擎还被配置为更新第一页表以包括第一映射。

9. 发明申请

US20140123146A1 EFFICIENT MEMORY VIRTUALIZATION IN MULTI-THREADED PROCESSING UNITS 审中-公开
公开(公告)号：US20140123146A1
公开(公告)日：2014-05-01
申请号：US13660799
申请日：2012-10-25
申请人： NVIDIA CORPORATION
发明人： Nick BARROW-WILLIAMS , Brian FAHS , Jerome F. DULUK, JR. , James Leroy DEMING , Timothy John PURCELL , Lucien DUNNING , Mark HAIRGROVE
IPC分类号： G06F9/46
CPC分类号： G06F9/5033 , G06F9/455 , G06F9/45533 , G06F9/45558 , G06F9/48 , G06F9/4881 , G06F9/50 , G06F9/5005 , G06F9/5027 , G06F9/5038 , G06F9/5044 , G06F9/505 , G06F12/1036 , G06F12/1045 , G06F12/109
摘要： A technique for simultaneously executing multiple tasks, each having an independent virtual address space, involves assigning an address space identifier (ASID) to each task and constructing each virtual memory access request to include both a virtual address and the ASID. During virtual to physical address translation, the ASID selects a corresponding page table, which includes virtual to physical address mappings for the ASID and associated task. Entries for a translation look-aside buffer (TLB) include both the virtual address and ASID to complete each mapping to a physical address. Deep scheduling of tasks sharing a virtual address space may be implemented to improve cache affinity for both TLB and data caches.

10. 发明申请

US20170161206A1 REPLAYING MEMORY TRANSACTIONS WHILE RESOLVING MEMORY ACCESS FAULTS 有权
公开(公告)号：US20170161206A1
公开(公告)日：2017-06-08
申请号：US15437400
申请日：2017-02-20
申请人： NVIDIA Corporation
发明人： James Leroy DEMING , Jerome F. DULUK, JR. , John MASHEY , Mark HAIRGROVE , Lucien DUNNING , Jonathon Stuart Ramsey EVANS , Samuel H. DUNCAN , Cameron BUSCHARDT , Brian FAHS
IPC分类号： G06F12/1027 , G06F9/46
CPC分类号： G06F12/1027 , G06F9/467 , G06F12/08 , G06F2212/301 , G06F2212/684
摘要： One embodiment of the present invention is a parallel processing unit (PPU) that includes one or more streaming multiprocessors (SMs) and implements a replay unit per SM. Upon detecting a page fault associated with a memory transaction issued by a particular SM, the corresponding replay unit causes the SM, but not any unaffected SMs, to cease issuing new memory transactions. The replay unit then stores the faulting memory transaction and any faulting in-flight memory transaction in a replay buffer. As page faults are resolved, the replay unit replays the memory transactions in the replay buffer—removing successful memory transactions from the replay buffer—until all of the stored memory transactions have successfully executed. Advantageously, the overall performance of the PPU is improved compared to conventional PPUs that, upon detecting a page fault, stop performing memory transactions across all SMs included in the PPU until the fault is resolved.

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