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1. 发明授权

US07493541B1 Method and system for performing built-in-self-test routines using an accumulator to store fault information 失效
标题翻译：使用累加器来执行内置自检程序来存储故障信息的方法和系统
公开(公告)号：US07493541B1
公开(公告)日：2009-02-17
申请号：US11824264
申请日：2007-06-29
申请人： Ghasi R. Agrawal , Mukesh K. Puri , William Schwarz
发明人： Ghasi R. Agrawal , Mukesh K. Puri , William Schwarz
IPC分类号： G01R31/28
CPC分类号： G11C29/56 , G11C29/56008
摘要： A test system includes a built-in self-test (BIST) circuit and a stress applicator for use in analyzing a memory array. The stress applicator applies a selective set of stress factors to the memory array, such as temperature and voltage conditions. The BIST circuit executes a test routine on the memory array to detect the presence of any faulty memory address locations that may arise under the prevailing stress condition. A full testing cycle involves iterative repetition of the functions performed by the stress applicator and BIST circuit, with variations in the stress factors across the testing iterations. An accumulator cumulatively stores the fault information generated by the BIST circuit during each testing iteration. Following completion of the testing cycle, a repair operation is performed by a built-in self-repair (BISR) circuit to remap the faulty memory address locations indicated by the accumulator to redundant memory address locations.
摘要翻译：测试系统包括内置的自检（BIST）电路和用于分析存储器阵列的应力施加器。应力施加器向存储器阵列施加选择性的一组应力因子，例如温度和电压条件。 BIST电路在存储器阵列上执行测试程序，以检测在当前应力条件下可能出现的任何故障存储器地址位置的存在。完整的测试周期包括由应力施加器和BIST电路执行的功能的迭代重复，并且跨越测试迭代的应力因子的变化。累加器在每个测试迭代期间累积地存储由BIST电路产生的故障信息。在完成测试周期之后，通过内置自修复（BISR）电路执行修复操作，将由累加器指示的故障存储器地址位置重新映射到冗余存储器地址位置。

2. 发明授权

US07260758B1 Method and system for performing built-in self-test routines using an accumulator to store fault information 有权
标题翻译：使用累加器执行内置自检程序来存储故障信息的方法和系统
公开(公告)号：US07260758B1
公开(公告)日：2007-08-21
申请号：US09949399
申请日：2001-09-07
申请人： Ghasi R. Agrawal , Mukesh K. Puri , William Schwarz
发明人： Ghasi R. Agrawal , Mukesh K. Puri , William Schwarz
IPC分类号： G01R31/28
CPC分类号： G11C29/56 , G11C29/56008
摘要： A test system includes a built-in self-test (BIST) circuit and a stress applicator for use in analyzing a memory array. The stress applicator applies a selective set of stress factors to the memory array, such as temperature and voltage conditions. The BIST circuit executes a test routine on the memory array to detect the presence of any faulty memory address locations that may arise under the prevailing stress condition. A full testing cycle involves iterative repetition of the functions performed by the stress applicator and BIST circuit, with variations in the stress factors across the testing iterations. An accumulator cumulatively stores the fault information generated by the BIST circuit during each testing iteration. Following completion of the testing cycle, a repair operation is performed by a built-in self-repair (BISR) circuit to remap the faulty memory address locations indicated by the accumulator to redundant memory address locations.
摘要翻译：测试系统包括内置自检（BIST）电路和用于分析存储器阵列的应力施加器。应力施加器向存储器阵列施加选择性的一组应力因子，例如温度和电压条件。 BIST电路在存储器阵列上执行测试程序，以检测在当前应力条件下可能出现的任何故障存储器地址位置的存在。完整的测试周期包括由应力施加器和BIST电路执行的功能的迭代重复，并且跨越测试迭代的应力因子的变化。累加器在每个测试迭代期间累积地存储由BIST电路产生的故障信息。在完成测试周期之后，通过内置自修复（BISR）电路执行修复操作，将由累加器指示的故障存储器地址位置重新映射到冗余存储器地址位置。

3. 发明授权

US06871297B2 Power-on state machine implementation with a counter to control the scan for products with hard-BISR memories 失效
标题翻译：开机状态机实现与计数器控制扫描产品与硬BISR记忆
公开(公告)号：US06871297B2
公开(公告)日：2005-03-22
申请号：US10120670
申请日：2002-04-11
申请人： Mukesh K. Puri , Ghasi R. Agrawal
发明人： Mukesh K. Puri , Ghasi R. Agrawal
IPC分类号： G06F11/00 , G11C29/00 , G11C29/16 , G11C29/44 , H04B1/74
CPC分类号： G11C29/44 , G11C29/16 , G11C29/4401 , G11C29/789
摘要： An apparatus comprising a controller circuit and a BISR assembly circuit. The controller circuit may be configured to present one or more control signals. The control signals may be configured to control one or more built-in self-test (BIST) and built-in self-repair (BISR) modes of operation. The BISR assembly circuit generally comprises one or more memory blocks each comprising a counter configured to generate a clock cycle count value in response to a repair solution during the BIST and BISR operations. The memory blocks may be remapped in response to the count values during one or more of the BISR operations.
摘要翻译：一种包括控制器电路和BISR组装电路的装置。控制器电路可以被配置为呈现一个或多个控制信号。控制信号可以被配置为控制一个或多个内置自检（BIST）和内置自修复（BISR）操作模式。 BISR组装电路通常包括一个或多个存储器块，每个存储块包括被配置为在BIST和BISR操作期间响应于修复解决方案产生时钟周期计数值的计数器。响应于在一个或多个BISR操作期间的计数值可以重新映射存储器块。

4. 发明授权

US07076699B1 Method for testing semiconductor devices having built-in self repair (BISR) memory 有权
标题翻译：用于测试具有内置自修复（BISR）存储器的半导体器件的方法
公开(公告)号：US07076699B1
公开(公告)日：2006-07-11
申请号：US09956302
申请日：2001-09-19
申请人： Mukesh K. Puri , Ghasi R. Agrawal , William Schwarz
发明人： Mukesh K. Puri , Ghasi R. Agrawal , William Schwarz
IPC分类号： G11C29/00
CPC分类号： G11C17/165 , G11C29/027 , G11C29/12015 , G11C29/44 , G11C29/4401 , G11C29/50 , G11C29/50012 , G11C29/50016 , G11C2029/4402
摘要： A method for testing semiconductor devices advantageously increases manufacturing yields. The method includes generating memory repair data for a wafer die by writing at least one predetermined digital bit pattern into a memory on the wafer die, reading the at least one predetermined digital bit pattern back out of the memory, comparing the at least one predetermined digital bit pattern read out from the memory against the at least one predetermined digital bit pattern written into the memory, and storing results of the comparison as the memory repair data. The writing and reading are performed a plurality of times, each time with a different voltage and clock frequency combination being applied to the wafer die. The memory repair data is programmed into the wafer die, and the wafer die is assembled into a packaged semiconductor device. The packaged semiconductor device is tested by causing the memory repair data programmed within the packaged semiconductor device to be transferred into the memory a plurality of times, each time with a different voltage and clock frequency combination being applied to the packaged semiconductor device.
摘要翻译：用于测试半导体器件的方法有利地提高了制造成品率。该方法包括通过将至少一个预定的数字位模式写入晶片管芯上的存储器来产生晶片管芯的存储器修复数据，将至少一个预定的数字位模式读出存储器，将至少一个预定的数字位模式从写入存储器的至少一个预定的数字位模式从存储器读出的位模式，并将比较的结果存储为存储器修复数据。执行写入和读取多次，每次以不同的电压和时钟频率组合施加到晶片管芯。将存储器修复数据编程到晶片管芯中，将晶片管芯组装成封装的半导体器件。通过使封装的半导体器件中编程的存储器修复数据被多次传送到封装的半导体器件中，每次都将不同的电压和时钟频率组合应用于封装的半导体器件。

5. 发明授权

US07536611B2 Hard BISR scheme allowing field repair and usage of reliability controller 失效
标题翻译：硬BISR方案允许现场维修和使用可靠性控制器
公开(公告)号：US07536611B2
公开(公告)日：2009-05-19
申请号：US10700177
申请日：2003-11-03
申请人： Mukesh K. Puri , Ghasi R. Agrawal , Tuan L. Phan
发明人： Mukesh K. Puri , Ghasi R. Agrawal , Tuan L. Phan
IPC分类号： G11C29/00
CPC分类号： G11C29/44 , G11C29/4401
摘要： A BISR scheme which provides for on-chip assessment of the amount of repair on a given memory and for the flagging of any device as a fail when the device exceeds a pre-determined limit. Preferably, a counter is built and loaded through a test pattern during production testing, and the counter establishes the threshold for pass/fail criteria. The BISR is configured to load a repair solution and then test the memories for any additional failures and if there are any, repair them (provided enough redundant elements are available). In addition, a reliability controller for BISR designs can be provided, where the reliability controller contains a register set and a number of counters at the chip-level which can be loaded through a test pattern during production tests, where one of the counters contains the number of memories to be allowed for repair.
摘要翻译： BISR方案，用于在给定存储器上进行片上修复量的评估，以及当设备超过预定限制时将任何设备标记为失败。优选地，在生产测试期间通过测试图案构建计数器并加载计数器，并且计数器建立通过/失败准则的阈值。 BISR被配置为加载修复解决方案，然后测试存储器的任何其他故障，如果有的话，修复它们（只要有足够的冗余元素可用）。此外，可以提供用于BISR设计的可靠性控制器，其中可靠性控制器包含在芯片级的寄存器组和多个计数器，其可以在生产测试期间通过测试模式加载，其中一个计数器包含允许修复的记忆数量。

6. 发明授权

US06928598B1 Scan method for built-in-self-repair (BISR) 失效
标题翻译：内置自我修复扫描方法（BISR）
公开(公告)号：US06928598B1
公开(公告)日：2005-08-09
申请号：US09880675
申请日：2001-06-13
申请人： Ghasi R. Agrawal , Mukesh K. Puri
发明人： Ghasi R. Agrawal , Mukesh K. Puri
IPC分类号： G01R31/28 , G01R31/3185 , G11C29/00
CPC分类号： G11C29/4401 , G01R31/318555 , G11C29/72 , G11C2029/3202
摘要： A system and method for protecting the values stored in a BISR repair block and, optionally, debugging the BISR repair logic without altering normal test flow is implemented by a circuit including a plurality of soft latches within the BISR repair block, the soft latches being coupled together to form a BISR scan chain for holding BISR repair information. A chip level scan enable signal and a scan hold control signal cooperate to control connection of the BISR scan chain to other scan chains during a scan test, so that the BSR repair information is held within the soft latches. A diagnose enable signal cooperating with the chip level scan enable signal and the scan hold control signal for enabling debugging of logic connecting the BISR scan chains.
摘要翻译：用于保护存储在BISR修复块中的值以及可选地调试BISR修复逻辑而不改变正常测试流的系统和方法由包括BISR修复块内的多个软锁存器的电路实现，所述软锁存器被耦合一起形成一个BISR扫描链，用于保存BISR修复信息。在扫描测试期间，芯片级扫描使能信号和扫描保持控制信号协调控制BISR扫描链与其他扫描链的连接，使得BSR修复信息保持在软锁存器内。诊断使能信号与芯片级扫描使能信号和扫描保持控制信号协同工作，以实现连接BISR扫描链的逻辑调试。

7. 发明授权

US06898143B2 Sharing fuse blocks between memories in hard-BISR 有权
标题翻译：在硬BISR中的内存之间共享熔丝块
公开(公告)号：US06898143B2
公开(公告)日：2005-05-24
申请号：US10647993
申请日：2003-08-26
申请人： Mukesh K. Puri , Ghasi R. Agrawal
发明人： Mukesh K. Puri , Ghasi R. Agrawal
IPC分类号： G11C7/00 , G11C29/00
CPC分类号： G11C29/88 , G11C29/4401 , G11C29/802
摘要： A BISR scheme which provides that fuse blocks are shared between memories to reduce hard-BISR implementation costs. The scheme includes a plurality of memories serially connected to a fuse controller. A plurality of fuse blocks are also serially connected to the fuse controller. There are more memory instances than there are fuse blocks, and the fuse controller is configured to allow the fuse blocks to be shared between memories. Preferably, each fuse block includes fuse elements which can be programmed with the memory instance number which needs to be repaired. The fuse block reduces routing congestion and is preferably configured to provide the flexibility of assigning any fuse block to any instance that needs repair. The programmable fuse elements are preferably loaded into a counter (which is preferably part of the fuse controller) which ensures that the correct block information gets loaded into the corresponding memory instance.
摘要翻译：一种BISR方案，其提供了在存储器之间共享的熔丝块，以减少硬性BISR的实施成本。该方案包括串联连接到熔丝控制器的多个存储器。多个熔丝块也串联连接到熔丝控制器。存在比存在熔丝块更多的存储器实例，并且熔丝控制器被配置为允许熔丝块在存储器之间共享。优选地，每个保险丝盒包括可以用需要修复的存储器实例编号的熔丝元件。熔断器块减少了路由拥塞，并且优选地被配置为提供将任何熔丝块分配给需要修复的任何实例的灵活性。可编程保险丝元件优选地被加载到计数器（其优选地是熔丝控制器的一部分），其确保正确的块信息被加载到相应的存储器实例中。

8. 发明授权

US07913125B2 BISR mode to test the redundant elements and regular functional memory to avoid test escapes 有权
标题翻译： BISR模式来测试冗余元素和常规功能内存，以避免测试转义
公开(公告)号：US07913125B2
公开(公告)日：2011-03-22
申请号：US10701332
申请日：2003-11-04
申请人： Ghasi R. Agrawal , Mukesh K. Puri
发明人： Ghasi R. Agrawal , Mukesh K. Puri
IPC分类号： G11C29/00
CPC分类号： G11C29/4401 , G11C29/24 , G11C29/44 , G11C29/838
摘要： A BISR mode and associated method for testing memory. All redundant elements of the memory including the ones which are not used are tested, and interaction between redundant elements of the memory and adjacent functional memory are checked. Repair information is used to repair the memory. In addition, redundant elements which are not needed to be used for repairing the memory are forced to be used, such as by faking defects to remap good elements with redundant elements.
摘要翻译：一种用于测试内存的BISR模式和相关方法。测试包括未使用的存储器的所有冗余元件，并检查存储器和相邻功能存储器的冗余元件之间的交互。修复信息用于修复内存。此外，强制使用不需要用于修复存储器的冗余元件，例如通过伪造缺陷以用冗余元件重新映射良好元素。

9. 发明授权

US07185243B1 Testing implementation suitable for built-in self-repair (BISR) memories 有权
标题翻译：测试实现适合内置自修复（BISR）存储器
公开(公告)号：US07185243B1
公开(公告)日：2007-02-27
申请号：US09872582
申请日：2001-06-04
申请人： Mukesh K. Puri , Ghasi R. Agrawal , Thompson W. Crosby
发明人： Mukesh K. Puri , Ghasi R. Agrawal , Thompson W. Crosby
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： B05B1/3026 , B05B1/3013 , F16K31/3855
摘要： A semiconductor memory testing implementation suitable for build-in self repair (BISR) memories provides, in one embodiment, a memory testing circuit configuration including an output register for receiving digital data. A plurality of shift registers serially output the digital data to be received by the output register. Each one of the plurality of shift registers includes a feedback path for enabling the digital data output by a corresponding one of the plurality of shift registers to be input back into the corresponding shift register in a same sequence as the digital data is output from the corresponding shift register.
摘要翻译：在一个实施例中，适用于内置自修复（BISR）存储器的半导体存储器测试实施例提供包括用于接收数字数据的输出寄存器的存储器测试电路配置。多个移位寄存器串行地输出要由输出寄存器接收的数字数据。多个移位寄存器中的每一个包括反馈路径，用于使得由多个移位寄存器中的相应一个移位寄存器输出的数字数据能够以与从相应的数字数据输出的数字数据相同的顺序输入到相应的移位寄存器移位寄存器

10. 发明授权

US06404700B1 Low power high density asynchronous memory architecture 有权
标题翻译：低功耗高密度异步存储器架构
公开(公告)号：US06404700B1
公开(公告)日：2002-06-11
申请号：US09880491
申请日：2001-06-13
申请人： Ghasi R. Agrawal
发明人： Ghasi R. Agrawal
IPC分类号： G11C800
CPC分类号： G11C8/16
摘要： An architecture for a low power, high density (smaller area) asynchronous memory comprises memory cells including a forward inverter and a feedback inverter disposed in a back-to-back arrangement (i.e., back-to-back inverters), two write access transistors, a read inverter, and a read access transistor. The architecture employs a double ended write into the memory cells wherein Write Bit Lines coupled to write access transistors are precharged to Vdd−Vtn, or, alternately Vdd, when the signal Write Enable (WE) is low (i.e., “0”).
摘要翻译：用于低功率，高密度（较小面积）异步存储器的架构包括存储单元，其包括以背对背布置（即背对背反向器）设置的正向反相器和反馈反相器，两个写入存取晶体管读取反相器和读取存取晶体管。该结构采用双端写入存储器单元，其中耦合到写存取晶体管的写位线被预充电到Vdd-Vtn，或者当信号写使能（WE）为低（即“0”）时交替地为Vdd。

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