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    • 9. 发明授权
    • Circuit and method for normalizing detector circuit
    • 用于归一化检测器电路的电路和方法
    • US5274578A
    • 1993-12-28
    • US850255
    • 1992-03-12
    • Jon C. NoethJames E. RobertsonTerry L. ZumwaltGlenn T. MortlandDavid O. Box
    • Jon C. NoethJames E. RobertsonTerry L. ZumwaltGlenn T. MortlandDavid O. Box
    • G01D3/02G01D18/00H04N5/33H04N5/365G06F15/31
    • G01D18/006G01D3/022H04N5/3655H04N5/33
    • A dynamic detector normalization circuit for normalizing detector output data using detector-error-correcting offset and gain coefficients that are updated in real time. The offset/gain coefficients are computed by a coefficient processor (20) at selected update intervals based on detector responses to a reference source. The coefficient processor averages detector reference responses over a number of update intervals to obtain updated offset/gain coefficients with greater precision than that available from the detector network. The detector normalization circuit (10) includes offset addition logic (12) and gain coefficient logic (14) for reading-out the offset/gain coefficients stored in respective RAMs (13, 15). For each detector output sample received by the detector normalization circuit (10), an offset addition operation 40 adds to the sample the MS bits of the offset coefficient. After the addition operation, the LS bits of the offset coefficient (representing increased precision available from the offset coefficient) are concatenated, and after underflow/overflow protection (42), an offset-corrected detector sample is obtained. A gain multiplication operation (50) multiplies the offset-corrected detector sample by the gain coefficient to obtain an offset/gain-corrected detector sample. After discarding LS bits representing unnecessary precision, and range-clipping (60), the normalization circuit (10) outputs normalized detector data with the desired precision. The detector normalization technique is described in connection with an exemplary application for normalizing thermal detector array output in a thermal imaging system.
    • 一种动态检测器归一化电路,用于使用实时更新的检测器误差校正偏移和增益系数对检测器输出数据进行归一化。 基于对参考源的检测器响应,偏移/增益系数由系数处理器(20)以选定的更新间隔计算。 系数处理器在多个更新间隔上对检测器参考响应进行平均,以获得比从检测器网络可用的精度更高的精度的更新的偏移/增益系数。 检测器归一化电路(10)包括用于读出存储在各个RAM(13,15)中的偏移/增益系数的偏移加法逻辑(12)和增益系数逻辑(14)。 对于由检测器归一化电路(10)接收到的每个检测器输出样本,偏移相加操作40向该采样添加偏移系数的MS位。 在相加操作之后,将偏移系数的LS位(表示从偏移系数得到的增加的精度)连接起来,并且在下溢/溢出保护(42)之后,获得偏移校正的检测器样本。 增益乘法运算(50)将经偏移校正的检测器样本乘以增益系数,以获得偏移/增益校正的检测器样本。 归一化电路(10)在丢弃表示不必要的精度的LS比特和范围限幅(60)之后,以所需的精度输出归一化的检测器数据。 结合用于在热成像系统中归一化热检测器阵列输出的示例性应用来描述检测器归一化技术。