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    • 1. 发明申请
    • LOCK-LESS BUFFER MANAGEMENT SCHEME FOR TELECOMMUNICATION NETWORK APPLICATIONS
    • 用于电信网络应用的LOCK-LESS BUFFER管理方案
    • US20120110223A1
    • 2012-05-03
    • US12914135
    • 2010-10-28
    • Mohammad R. KhawerLina So
    • Mohammad R. KhawerLina So
    • G06F5/00
    • G06F9/5011H04L49/901H04L49/9047H04L49/9073
    • A buffer management mechanism in a multi-core processor for use on a modem in a telecommunications network is described herein. The buffer management mechanism includes a buffer module that provides buffer management services for one or more Layer 2 applications, wherein the buffer module at least provides a user space application interface to application software running in user space. The buffer management mechanism also includes a buffer manager that manages a plurality of separate pools of tokens, wherein the tokens comprise pointers to memory areas in external memory. In addition, the buffer management mechanism includes a custom driver that manages Data Path Acceleration Architecture (DPAA) resources including buffer pools and frame queues to be used for user plane data distributing.
    • 这里描述了用于在电信网络中的调制解调器上使用的多核处理器中的缓冲器管理机制。 缓冲器管理机制包括缓冲器模块,用于为一个或多个第2层应用提供缓冲管理服务,其中缓冲器模块至少向在用户空间中运行的应用软件提供用户空间应用接口。 缓冲器管理机制还包括一个缓冲管理器,该缓冲管理器管理多个单独的令牌池,其中令牌包括指向外部存储器中的存储器区域的指针。 另外,缓冲管理机制包括一个管理数据路径加速体系结构(DPAA)资源的自定义驱动程序,包括用于用户平面数据分发的缓冲池和帧队列。
    • 2. 发明申请
    • LOCK-LESS AND ZERO COPY MESSAGING SCHEME FOR TELECOMMUNICATION NETWORK APPLICATIONS
    • 用于电信网络应用的LOCK-LESS和ZERO COPY MESSING方案
    • US20120120965A1
    • 2012-05-17
    • US12945146
    • 2010-11-12
    • Mohammad R. KhawerLina So
    • Mohammad R. KhawerLina So
    • H04L12/56G06F13/24
    • H04L49/9031
    • A computer-implemented system and method for a lock-less, zero data copy messaging mechanism in a multi-core processor for use on a modem in a telecommunications network are described herein. The method includes, for each of a plurality of processing cores, acquiring a kernel to user-space (K-U) mapped buffer and corresponding buffer descriptor, inserting a data packet into the buffer; and inserting the buffer descriptor into a circular buffer. The method further includes creating a frame descriptor containing the K-U mapped buffer pointer, inserting the frame descriptor onto a frame queue specified by a dynamic PCD rule mapping IP addresses to frame queues, and creating a buffer descriptor from the frame descriptor.
    • 这里描述了用于在电信网络中的调制解调器上使用的多核处理器中的无锁零零数据复制消息传送机制的计算机实现的系统和方法。 该方法包括:对于多个处理核心中的每一个,对用户空间(K-U)映射缓冲器和对应的缓冲器描述符获取内核,将数据包插入到缓冲器中; 并将缓冲区描述符插入循环缓冲区。 该方法还包括创建包含K-U映射缓冲器指针的帧描述符,将帧描述符插入到由映射IP地址到帧队列的动态PCD规则指定的帧队列上,以及从帧描述符创建缓冲器描述符。
    • 3. 发明授权
    • Lock-less and zero copy messaging scheme for telecommunication network applications
    • 电信网络应用的无锁和零复制消息传递方案
    • US08737417B2
    • 2014-05-27
    • US12945146
    • 2010-11-12
    • Mohammad R. KhawerLina So
    • Mohammad R. KhawerLina So
    • H04L12/54
    • H04L49/9031
    • A computer-implemented system and method for a lock-less, zero data copy messaging mechanism in a multi-core processor for use on a modem in a telecommunications network are described herein. The method includes, for each of a plurality of processing cores, acquiring a kernel to user-space (K-U) mapped buffer and corresponding buffer descriptor, inserting a data packet into the buffer; and inserting the buffer descriptor into a circular buffer. The method further includes creating a frame descriptor containing the K-U mapped buffer pointer, inserting the frame descriptor onto a frame queue specified by a dynamic PCD rule mapping IP addresses to frame queues, and creating a buffer descriptor from the frame descriptor.
    • 这里描述了用于在电信网络中的调制解调器上使用的多核处理器中的无锁零零数据复制消息传送机制的计算机实现的系统和方法。 该方法包括:对于多个处理核心中的每一个,对用户空间(K-U)映射缓冲器和对应的缓冲器描述符获取内核,将数据包插入到缓冲器中; 并将缓冲区描述符插入循环缓冲区。 该方法还包括创建包含K-U映射缓冲器指针的帧描述符,将帧描述符插入到由映射IP地址到帧队列的动态PCD规则指定的帧队列上,以及从帧描述符创建缓冲器描述符。
    • 4. 发明授权
    • Lock-less buffer management scheme for telecommunication network applications
    • 电信网络应用的无锁缓存管理方案
    • US08504744B2
    • 2013-08-06
    • US12914135
    • 2010-10-28
    • Mohammad R. KhawerLina So
    • Mohammad R. KhawerLina So
    • G06F3/00G06F5/00
    • G06F9/5011H04L49/901H04L49/9047H04L49/9073
    • A buffer management mechanism in a multi-core processor for use on a modem in a telecommunications network is described herein. The buffer management mechanism includes a buffer module that provides buffer management services for one or more Layer 2 applications, wherein the buffer module at least provides a user space application interface to application software running in user space. The buffer management mechanism also includes a buffer manager that manages a plurality of separate pools of tokens, wherein the tokens comprise pointers to memory areas in external memory. In addition, the buffer management mechanism includes a custom driver that manages Data Path Acceleration Architecture (DPAA) resources including buffer pools and frame queues to be used for user plane data distributing.
    • 这里描述了用于在电信网络中的调制解调器上使用的多核处理器中的缓冲器管理机制。 缓冲器管理机制包括缓冲器模块,用于为一个或多个第2层应用提供缓冲管理服务,其中缓冲器模块至少向在用户空间中运行的应用软件提供用户空间应用接口。 缓冲器管理机制还包括一个缓冲管理器,该缓冲管理器管理多个单独的令牌池,其中令牌包括指向外部存储器中的存储器区域的指针。 另外,缓冲管理机制包括一个管理数据路径加速体系结构(DPAA)资源的自定义驱动程序,包括用于用户平面数据分发的缓冲池和帧队列。
    • 6. 发明授权
    • Method and system for improved multi-cell support on a single modem board
    • 在单个调制解调器板上改进多单元支持的方法和系统
    • US08861434B2
    • 2014-10-14
    • US12955202
    • 2010-11-29
    • Mohammad R. KhawerMugur Abulius
    • Mohammad R. KhawerMugur Abulius
    • H04L29/00H04L12/70
    • H04L49/90
    • A system for providing multi-cell support within a single SMP partition in a telecommunications network is disclosed. The typically includes a modem board and a multi-core processor having a plurality of processor cores, wherein the multi-core processor is configured to disable non-essential interrupts arriving on a plurality of data plane cores and route the non-essential interrupts to a plurality of control plane cores. Optionally, the multi-core processor may be configured so that all non-real-time threads and processes are bound to processor cores that are dedicated for all control plane activities and processor cores that are dedicated for all data plane activities will not host or run any threads that are not directly needed for data path implementation or Layer 2 processing.
    • 公开了一种用于在电信网络中的单个SMP分区内提供多小区支持的系统。 通常包括调制解调器板和具有多个处理器核心的多核处理器,其中多核处理器被配置为禁止到达多个数据平面核心的非必要中断,并将非必要中断路由到 多个控制平面核心。 可选地,多核处理器可以被配置为使得所有非实时线程和进程都被绑定到专用于所有控制平面活动的处理器核心,专用于所有数据平面活动的处理器核心将不会托管或运行 数据路径实现或二层处理不直接需要的任何线程。