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1. 发明授权

US09196611B2 Reduced substrate coupling for inductors in semiconductor devices 有权
标题翻译：降低半导体器件中电感器的衬底耦合
公开(公告)号：US09196611B2
公开(公告)日：2015-11-24
申请号：US14250519
申请日：2014-04-11
申请人： Harry Hak-Lay Chuang , Ming Zhu , Lee-Wee Teo
发明人： Harry Hak-Lay Chuang , Ming Zhu , Lee-Wee Teo
IPC分类号： H01L31/119 , H01L27/06 , H01L23/522 , H01L27/02 , H01L27/08
CPC分类号： H01L27/0617 , H01L23/5227 , H01L27/0207 , H01L27/08 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides reduced substrate coupling for inductors in semiconductor devices. A method of fabricating a semiconductor device having reduced substrate coupling includes providing a substrate having a first region and a second region. The method also includes forming a first gate structure over the first region and a second gate structure over the second region, wherein the first and second gate structures each include a dummy gate. The method next includes forming an inter layer dielectric (ILD) over the substrate and forming a photoresist (PR) layer over the second gate structure. Then, the method includes removing the dummy gate from the first gate structure, thereby forming a trench and forming a metal gate in the trench so that a transistor may be formed in the first region, which includes a metal gate, and an inductor component may be formed over the second region, which does not include a metal gate.
摘要翻译：本公开为半导体器件中的电感器提供了减少的衬底耦合。制造具有减小的衬底耦合的半导体器件的方法包括提供具有第一区域和第二区域的衬底。该方法还包括在第一区域上形成第一栅极结构，在第二区域上形成第二栅极结构，其中第一和第二栅极结构各自包括虚拟栅极。该方法接下来包括在衬底上形成层间电介质（ILD），并在第二栅极结构上形成光刻胶（PR）层。然后，该方法包括从第一栅极结构中去除伪栅极，由此形成沟槽并在沟槽中形成金属栅极，使得晶体管可以形成在包括金属栅极的第一区域中，并且电感器元件可以形成在不包括金属栅极的第二区域上。

2. 发明申请

US20140054711A1 System and Method for a Vertical Tunneling Field-Effect Transistor Cell 有权
标题翻译：垂直隧道场效应晶体管单元的系统和方法
公开(公告)号：US20140054711A1
公开(公告)日：2014-02-27
申请号：US13594289
申请日：2012-08-24
申请人： Harry Hak-Lay Chuang , Ming Zhu
发明人： Harry Hak-Lay Chuang , Ming Zhu
IPC分类号： H01L27/088 , H01L21/336 , H01L29/78
CPC分类号： H01L29/7391 , H01L21/823418 , H01L21/823885 , H01L27/092 , H01L29/0657 , H01L29/42356 , H01L29/4238 , H01L29/7889
摘要： A semiconductor device cell is disclosed. The semiconductor device cell includes a transistor gate having a gating surface and a contacting surface and a source region contacted by a source contact. The semiconductor device cell further includes a drain region contacted by a drain contact, wherein the drain contact is not situated opposite the source contact with respect to the gating surface of the transistor gate. Additional semiconductor device cells in which the gate contact is closer to the source contact than to the drain contact are disclosed.
摘要翻译：公开了一种半导体器件单元。半导体器件单元包括晶体管栅极，其具有门控表面和接触表面以及与源极接触的源极区域。半导体器件单元还包括与漏极接触接触的漏极区，其中漏极接触件不相对于晶体管栅极的选通表面与源极接触相对。公开了其中栅极接触比漏极接触更靠近源极接触的其它半导体器件单元。

3. 发明申请

US20140042524A1 Device with a Vertical Gate Structure 有权
标题翻译：具有垂直门结构的装置
公开(公告)号：US20140042524A1
公开(公告)日：2014-02-13
申请号：US13568997
申请日：2012-08-07
申请人： Hak-Lay Chuang , Ming Zhu , Yi-Ren Chen
发明人： Hak-Lay Chuang , Ming Zhu , Yi-Ren Chen
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66795 , H01L21/28114 , H01L21/76885 , H01L21/823821 , H01L21/823828 , H01L21/823885 , H01L29/42376
摘要： A device includes a wafer substrate, a conical frustum structure formed in the wafer substrate, and a gate all-around (GAA) structure circumscribing the middle portion of the conical frustum structure. The conical frustum structure includes a drain formed at a bottom portion of the conical frustum, a source formed at a top portion of the vertical conical frustum, and a channel formed at a middle portion of the conical frustum connecting the source and the drain. The GAA structure overlaps with the source at one side of the GAA structure, crosses over the channel, and overlaps with the drain at another side of the GAA structure.
摘要翻译：一种器件包括晶片衬底，形成在晶片衬底中的锥形截头锥体结构，以及围绕锥形截头锥体结构的中间部分的栅极全能（GAA）结构。锥形截头锥体结构包括形成在锥形截头锥体的底部处的排水口，形成在垂直锥形截头锥体的顶部处的源和形成在连接源极和漏极的锥形截头锥体的中间部分处的通道。 GAA结构与GAA结构一侧的源重叠，与沟道交叉，并与GAA结构另一侧的漏极重叠。

4. 发明申请

US20130264652A1 Cost-Effective Gate Replacement Process 有权
公开(公告)号：US20130264652A1
公开(公告)日：2013-10-10
申请号：US13440848
申请日：2012-04-05
申请人： Ming Zhu , Jyun-Ming Lin , Wei Cheng Wu , Bao-Ru Young , Hak-Lay Chuang
发明人： Ming Zhu , Jyun-Ming Lin , Wei Cheng Wu , Bao-Ru Young , Hak-Lay Chuang
IPC分类号： H01L21/28 , H01L21/283 , H01L27/092
CPC分类号： H01L29/4941 , H01L21/28088 , H01L21/283 , H01L21/28518 , H01L21/76814 , H01L21/76843 , H01L21/76855 , H01L21/823443 , H01L21/82345 , H01L21/823842 , H01L21/82385 , H01L27/092 , H01L27/0922 , H01L29/401 , H01L29/4236 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/6659
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a first gate structure and a second gate structure over a substrate. The first and second gate structures each include a high-k dielectric layer located over the substrate, a capping layer located over the high-k dielectric layer, an N-type work function metal layer located over the capping layer, and a polysilicon layer located over the N-type work function metal layer. The method includes forming an inter-layer dielectric (ILD) layer over the substrate, the first gate structure, and the second gate structure. The method includes polishing the ILD layer until a surface of the ILD layer is substantially co-planar with surfaces of the first gate structure and the second gate structure. The method includes replacing portions of the second gate structure with a metal gate. A silicidation process is then performed to the semiconductor device.

5. 发明申请

US20130260547A1 METHOD OF FABRICATING A METAL GATE SEMICONDUCTOR DEVICE 有权
标题翻译：制造金属栅极半导体器件的方法
公开(公告)号：US20130260547A1
公开(公告)日：2013-10-03
申请号：US13434344
申请日：2012-03-29
申请人： Sheng-Chen Chung , Ming Zhu , Jyun-Ming Lin , Bao-Ru Young , Hak-Lay Chuang
发明人： Sheng-Chen Chung , Ming Zhu , Jyun-Ming Lin , Bao-Ru Young , Hak-Lay Chuang
IPC分类号： H01L21/336
CPC分类号： H01L21/823842 , H01L21/28088 , H01L21/28202 , H01L21/82385 , H01L21/823857 , H01L29/4966 , H01L29/517
摘要： A method of semiconductor device fabrication including providing a substrate having a gate dielectric layer such as a high-k dielectric disposed thereon. A tri-layer element is formed on the gate dielectric layer. The tri-layer element includes a first capping layer, a second capping layer, and a metal gate layer interposing the first and second capping layer. One of an nFET and a pFET gate structure are formed using the tri-layer element, for example, the second capping layer and the metal gate layer may form a work function layer for one of an nFET and a pFET device. The first capping layer may be a sacrificial layer used to pattern the metal gate layer.
摘要翻译：一种半导体器件制造方法，包括提供具有栅极电介质层的衬底，例如设置在其上的高k电介质。在栅介质层上形成三层元件。三层元件包括第一覆盖层，第二覆盖层和插入第一和第二覆盖层的金属栅极层。使用三层元件形成nFET和pFET栅极结构之一，例如，第二覆盖层和金属栅极层可以形成nFET和pFET器件中的一个的功函数层。第一覆盖层可以是用于图案化金属栅极层的牺牲层。

6. 发明授权

US08378428B2 Metal gate structure of a semiconductor device 有权
标题翻译：半导体器件的金属栅极结构
公开(公告)号：US08378428B2
公开(公告)日：2013-02-19
申请号：US12893338
申请日：2010-09-29
申请人： Han-Guan Chew , Lee-Wee Teo , Ming Zhu , Bao-Ru Young , Harry-Hak-Lay Chuang
发明人： Han-Guan Chew , Lee-Wee Teo , Ming Zhu , Bao-Ru Young , Harry-Hak-Lay Chuang
IPC分类号： H01L21/02
CPC分类号： H01L21/823842 , H01L21/28079 , H01L21/28088 , H01L21/82385 , H01L29/66545
摘要： The applications discloses a semiconductor device comprising a substrate having a first active region, a second active region, and an isolation region having a first width interposed between the first and second active regions; a P-metal gate electrode over the first active region and extending over at least ⅔ of the first width of the isolation region; and an N-metal gate electrode over the second active region and extending over no more than ⅓ of the first width. The N-metal gate electrode is electrically connected to the P-metal gate electrode over the isolation region.
摘要翻译：应用公开了一种半导体器件，其包括具有第一有源区，第二有源区和具有介于第一和第二有源区之间的第一宽度的隔离区的衬底; 在所述第一有源区上方的P金属栅电极，并且延伸至所述隔离区的第一宽度的至少;; 以及在第二有源区上方的N极金属栅电极，并延伸超过第一宽度的1/3。 N型金属栅电极在隔离区域上电连接到P金属栅电极。

7. 发明申请

US20130032884A1 INTEGRATED CIRCUIT DEVICE HAVING DEFINED GATE SPACING AND METHOD OF DESIGNING AND FABRICATING THEREOF 有权
标题翻译：具有定义的间隙的集成电路装置及其设计和制造方法
公开(公告)号：US20130032884A1
公开(公告)日：2013-02-07
申请号：US13195628
申请日：2011-08-01
申请人： Hak-Lay Chuang , Ming Zhu , Po-Nien Chen , Bao-Ru Young
发明人： Hak-Lay Chuang , Ming Zhu , Po-Nien Chen , Bao-Ru Young
IPC分类号： H01L27/088 , G06F17/50 , H01L21/336
CPC分类号： H01L29/42376 , G06F17/5068 , G06F17/5072 , G06F17/5081 , H01L21/823437 , H01L27/0207 , H01L27/0218 , H01L27/088 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/785 , H01L2223/58
摘要： A device, and method of fabricating and/or designing such a device, including a first gate structure having a width (W) and a length (L) and a second gate structure separated from the first gate structure by a distance greater than: (√{square root over (W*W+L*L)})/10. The second gate structure is a next adjacent gate structure to the first gate structure. A method and apparatus for designing an integrated circuit including implementing a design rule defining the separation of gate structures is also described. In embodiments, the distance of separation is implemented for gate structures that are larger relative to other gate structures on the substrate (e.g., greater than 3 μm2).
摘要翻译：一种器件，以及制造和/或设计这种器件的方法，包括具有宽度（W）和长度（L）的第一栅极结构以及与第一栅极结构分离大于的距离的第二栅极结构： √{平方根（W * W + L * L）}）/ 10。第二栅极结构是与第一栅极结构相邻的下一个栅极结构。还描述了一种用于设计集成电路的方法和装置，包括实现限定栅极结构分离的设计规则。在实施例中，对于相对于衬底上的其它栅极结构（例如，大于3μm2）较大的栅极结构，实现分离距离。

8. 发明授权

US08349678B2 Laterally diffused metal oxide semiconductor transistor with partially unsilicided source/drain 有权
标题翻译：具有部分非硅源极/漏极的侧向扩散的金属氧化物半导体晶体管
公开(公告)号：US08349678B2
公开(公告)日：2013-01-08
申请号：US12701824
申请日：2010-02-08
申请人： Harry-Hak-Lay Chuang , Lee-Wee Teo , Ming Zhu
发明人： Harry-Hak-Lay Chuang , Lee-Wee Teo , Ming Zhu
IPC分类号： H01L21/336
CPC分类号： H01L29/66659 , H01L21/28079 , H01L21/28088 , H01L21/28185 , H01L29/41775 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/78
摘要： A method of fabricating a laterally diffused metal oxide semiconductor (LDMOS) transistor includes forming a dummy gate over a substrate. A source and a drain are formed over the substrate on opposite sides of the dummy gate. A first silicide is formed on the source. A second silicide is formed on the drain so that an unsilicided region of at least one of the drain or the source is adjacent to the dummy gate. The unsilicided region of the drain provides a resistive region capable of sustaining a voltage load suitable for a high voltage LDMOS application. A replacement gate process is performed on the dummy gate to form a gate.
摘要翻译：制造横向扩散的金属氧化物半导体（LDMOS）晶体管的方法包括在衬底上形成虚拟栅极。在虚拟栅极的相对侧上的衬底上形成源极和漏极。在源上形成第一硅化物。在漏极上形成第二硅化物，使得至少一个漏极或源极的非硅化区域与虚拟栅极相邻。漏极的非硅化区域提供能够承受适合于高电压LDMOS应用的电压负载的电阻区域。在虚拟栅极上执行替换栅极处理以形成栅极。

9. 发明申请

US20120319238A1 Large Dimension Device and Method of Manufacturing Same in Gate Last Process 有权
标题翻译：大尺寸装置及制造方法相同于闸门最后工序
公开(公告)号：US20120319238A1
公开(公告)日：2012-12-20
申请号：US13160096
申请日：2011-06-14
申请人： Hak-Lay Chuang , Ming Zhu
发明人： Hak-Lay Chuang , Ming Zhu
IPC分类号： H01L29/02 , H01L21/28
CPC分类号： H01L28/60 , H01L21/823437 , H01L29/66181 , H01L29/94
摘要： An integrated circuit device and methods of manufacturing the same are disclosed. In an example, integrated circuit device includes a capacitor having a doped region disposed in a semiconductor substrate, a dielectric layer disposed over the doped region, and an electrode disposed over the dielectric layer. At least one post feature embedded in the electrode.
摘要翻译：公开了一种集成电路器件及其制造方法。在一个示例中，集成电路器件包括具有设置在半导体衬底中的掺杂区域的电容器，设置在掺杂区域上的电介质层和设置在电介质层上的电极。至少有一个帖子功能嵌入电极。

10. 发明申请

US20120299115A1 SEMICONDUCTOR STRUCTURE WITH SUPPRESSED STI DISHING EFFECT AT RESISTOR REGION 有权
标题翻译：半导体结构在电阻区域具有抑制性的磁带扫描效应
公开(公告)号：US20120299115A1
公开(公告)日：2012-11-29
申请号：US13115488
申请日：2011-05-25
申请人： Hak-Lay Chuang , Ming Zhu , Lee-Wee Teo , Bao-Ru Young
发明人： Hak-Lay Chuang , Ming Zhu , Lee-Wee Teo , Bao-Ru Young
IPC分类号： H01L21/762 , H01L27/06
CPC分类号： H01L27/0629 , H01L21/31055 , H01L21/31111 , H01L21/76224 , H01L28/20 , H01L29/0649
摘要： A method includes forming a first isolation feature of a first width and a second isolation feature of a second width in a substrate, the first width being substantially greater than the second width; forming an implantation mask on the substrate, wherein the implantation mask covers the first isolation feature and exposes the second isolation feature; performing an ion implantation process to the substrate using the implantation mask; and thereafter performing an etching process to the substrate.
摘要翻译：一种方法包括在衬底中形成第一宽度的第一隔离特征和第二宽度的第二隔离特征，第一宽度基本上大于第二宽度; 在所述衬底上形成注入掩模，其中所述注入掩模覆盖所述第一隔离特征并暴露所述第二隔离特征; 使用所述注入掩模对所述衬底进行离子注入工艺; 然后对基板进行蚀刻处理。

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