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1. 发明授权

US08683291B2 High throughput frame check sequence module architecture 有权
标题翻译：高吞吐量帧校验序列模块架构
公开(公告)号：US08683291B2
公开(公告)日：2014-03-25
申请号：US13161796
申请日：2011-06-16
申请人： Mikhail I. Grinchuk , Anatoli A. Bolotov , Lav Ivanovic
发明人： Mikhail I. Grinchuk , Anatoli A. Bolotov , Lav Ivanovic
IPC分类号： H03M13/00 , G11C29/00
CPC分类号： G06F11/1004 , H03M13/091 , H03M13/616
摘要： Described embodiments provide for a frame check sequence (FCS) module with a cyclic redundancy check (CRC) unit that receives a data block (padded, if necessary, to a maximum width) and a first state vector and computes an internal vector based on an extended CRC transition matrix. The FCS module further includes a set of matrix units, each matrix unit configured to multiply the internal vector by a corresponding correction matrix wherein the multiplications result in a set of products. A multiplexer selects, by a control signal determined by a maximum number of bytes and the original width, a second state vector from the set of products.
摘要翻译：描述的实施例提供具有循环冗余校验（CRC）单元的帧校验序列（FCS）模块，其接收数据块（如果需要，填充到最大宽度）和第一状态向量，并且基于扩展CRC转换矩阵。 FCS模块还包括一组矩阵单元，每个矩阵单元被配置为将内部矢量乘以相应的校正矩阵，其中乘法产生一组乘积。复用器通过由最大字节数和原始宽度确定的控制信号选择来自该组乘积的第二状态向量。

2. 发明申请

US20120324319A1 HIGH THROUGHPUT FRAME CHECK SEQUENCE MODULE ARCHITECTURE 有权
标题翻译：高通道帧检查序列模块架构
公开(公告)号：US20120324319A1
公开(公告)日：2012-12-20
申请号：US13161796
申请日：2011-06-16
申请人： Mikhail I. Grinchuk , Anatoli A. Bolotov , Lav Ivanovic
发明人： Mikhail I. Grinchuk , Anatoli A. Bolotov , Lav Ivanovic
IPC分类号： H03M13/09 , G06F11/10
CPC分类号： G06F11/1004 , H03M13/091 , H03M13/616
摘要： Described embodiments provide for a frame check sequence (FCS) module with a cyclic redundancy check (CRC) unit that receives a data block (padded, if necessary, to a maximum width) and a first state vector and computes an internal vector based on an extended CRC transition matrix. The FCS module further includes a set of matrix units, each matrix unit configured to multiply the internal vector by a corresponding correction matrix wherein the multiplications result in a set of products. A multiplexer selects, by a control signal determined by a maximum number of bytes and the original width, a second state vector from the set of products.
摘要翻译：描述的实施例提供具有循环冗余校验（CRC）单元的帧校验序列（FCS）模块，其接收数据块（如果需要，填充到最大宽度）和第一状态向量，并且基于扩展CRC转换矩阵。 FCS模块还包括一组矩阵单元，每个矩阵单元被配置为将内部矢量乘以相应的校正矩阵，其中乘法产生一组乘积。复用器通过由最大字节数和原始宽度确定的控制信号选择来自该组乘积的第二状态向量。

3. 发明申请

US20120076298A1 UNIFIED ARCHITECTURE FOR CRYPTO FUNCTIONAL UNITS 有权
标题翻译：统一的结构功能单位
公开(公告)号：US20120076298A1
公开(公告)日：2012-03-29
申请号：US12892455
申请日：2010-09-28
申请人： Anatoli A. Bolotov , Mikhail I. Grinchuk , Lav Ivanovic , Igor Kucherenko , Alexei Galatenko
发明人： Anatoli A. Bolotov , Mikhail I. Grinchuk , Lav Ivanovic , Igor Kucherenko , Alexei Galatenko
IPC分类号： H04K1/00
CPC分类号： H04L9/0643 , H04L9/0631 , H04L2209/125
摘要： In described embodiments, a unified Crypto Functional Unit (CFU) block architecture provides a capability for advanced communication processors to provide parallel and concurrent processing of multiple crypto operations/transactions within high-speed hardware to support different security standards (e.g. from IPsec, 3GPP). In particular, each CFU block of the unified CFU block architecture comprises a FIFO-based interface, switch, and wrapped cipher/hasher. The unified CFU block architecture allows for drop-in solutions for cipher blocks in ASIC designs with crypto function blocks.
摘要翻译：在所描述的实施例中，统一的加密功能单元（CFU）块架构为高级通信处理器提供了在高速硬件内提供并行和并发处理多个加密操作/事务的能力，以支持不同的安全标准（例如，从IPsec，3GPP）。特别地，统一CFU块架构的每个CFU块包括基于FIFO的接口，交换机和封装的加密/哈希器。统一的CFU块架构允许在具有加密功能块的ASIC设计中的密码块的插入式解决方案。

4. 发明授权

US08302083B2 Architecture and implementation method of programmable arithmetic controller for cryptographic applications 失效
标题翻译：用于加密应用的可编程运算控制器的架构和实现方法
公开(公告)号：US08302083B2
公开(公告)日：2012-10-30
申请号：US12321643
申请日：2009-01-23
申请人： Anatoli A. Bolotov , Mikhail I. Grinchuk , Lav Ivanovic , Alexei Galatenko
发明人： Anatoli A. Bolotov , Mikhail I. Grinchuk , Lav Ivanovic , Alexei Galatenko
IPC分类号： G06F15/76 , G06F9/302 , G06F9/45
CPC分类号： G06F9/3001 , G06F21/72
摘要： An architecture includes a controller. The controller is configured to receive a microprogram. The microprogram is configured for performing at least one of hierarchical or a sequence of polynomial computations. The architecture also includes an arithmetic logic unit (ALU) communicably coupled to the controller. The ALU is controlled by the controller. Additionally, the microprogram is compiled prior to execution by the controller, the microprogram is compiled into a plurality of binary tables, and the microprogram is programmed in a command language in which each command includes a first portion for indicating at least one of a command or data transferred to the ALU, and a second portion for including a control command to the controller. The architecture and implementation of the programmable controller may be for cryptographic applications, including those related to public key cryptography.
摘要翻译：一个架构包括一个控制器。控制器被配置为接收微程序。微程序被配置用于执行多项式计算的分层或序列中的至少一个。该架构还包括可通信地耦合到控制器的算术逻辑单元（ALU）。 ALU由控制器控制。此外，微程序在控制器执行之前被编译，微程序被编译成多个二进制表，并且微程序以命令语言编程，其中每个命令包括用于指示命令或命令中的至少一个的第一部分，传送到ALU的数据，以及用于向控制器包括控制命令的第二部分。可编程控制器的架构和实现可以用于加密应用，包括与公开密码密码相关的应用。

5. 发明申请

US20100191935A1 Architecture and implementation method of programmable arithmetic controller for cryptographic applications 失效
标题翻译：用于加密应用的可编程运算控制器的架构和实现方法
公开(公告)号：US20100191935A1
公开(公告)日：2010-07-29
申请号：US12321643
申请日：2009-01-23
申请人： Anatoli A. Bolotov , Mikhail I. Grinchuk , Lav Ivanovic , Alexei Galatenko
发明人： Anatoli A. Bolotov , Mikhail I. Grinchuk , Lav Ivanovic , Alexei Galatenko
IPC分类号： G06F15/76 , G06F9/302
CPC分类号： G06F9/3001 , G06F21/72
摘要： An architecture includes a controller. The controller is configured to receive a microprogram. The microprogram is configured for performing at least one of hierarchical or a sequence of polynomial computations. The architecture also includes an arithmetic logic unit (ALU) communicably coupled to the controller. The ALU is controlled by the controller. Additionally, the microprogram is compiled prior to execution by the controller, the microprogram is compiled into a plurality of binary tables, and the microprogram is programmed in a command language in which each command includes a first portion for indicating at least one of a command or data transferred to the ALU, and a second portion for including a control command to the controller. The architecture and implementation of the programmable controller may be for cryptographic applications, including those related to public key cryptography.
摘要翻译：一个架构包括一个控制器。控制器被配置为接收微程序。微程序被配置用于执行多项式计算的分层或序列中的至少一个。该架构还包括可通信地耦合到控制器的算术逻辑单元（ALU）。 ALU由控制器控制。此外，微程序在控制器执行之前被编译，微程序被编译成多个二进制表，并且微程序以命令语言编程，其中每个命令包括用于指示命令或命令中的至少一个的第一部分，传送到ALU的数据，以及用于向控制器包括控制命令的第二部分。可编程控制器的架构和实现可以用于加密应用，包括与公开密码密码相关的应用。

6. 发明授权

US08831221B2 Unified architecture for crypto functional units 有权
标题翻译：加密功能单元的统一架构
公开(公告)号：US08831221B2
公开(公告)日：2014-09-09
申请号：US12892455
申请日：2010-09-28
申请人： Anatoli A. Bolotov , Mikhail I. Grinchuk , Lav Ivanovic , Igor Kucherenko , Alexei Galatenko
发明人： Anatoli A. Bolotov , Mikhail I. Grinchuk , Lav Ivanovic , Igor Kucherenko , Alexei Galatenko
IPC分类号： H04L9/00 , H04L9/06
CPC分类号： H04L9/0643 , H04L9/0631 , H04L2209/125
摘要： In described embodiments, a unified Crypto Functional Unit (CFU) block architecture provides a capability for advanced communication processors to provide parallel and concurrent processing of multiple crypto operations/transactions within high-speed hardware to support different security standards (e.g. from IPsec, 3GPP). In particular, each CFU block of the unified CFU block architecture comprises a FIFO-based interface, switch, and wrapped cipher/hasher. The unified CFU block architecture allows for drop-in solutions for cipher blocks in ASIC designs with crypto function blocks.
摘要翻译：在所描述的实施例中，统一的加密功能单元（CFU）块架构为高级通信处理器提供了在高速硬件内提供并行和并发处理多个加密操作/事务的能力，以支持不同的安全标准（例如，从IPsec，3GPP）。特别地，统一CFU块架构的每个CFU块包括基于FIFO的接口，交换机和封装的加密/哈希器。统一的CFU块架构允许在具有加密功能块的ASIC设计中的密码块的插入式解决方案。

7. 发明授权

US08898539B2 Correcting errors in miscorrected codewords using list decoding 有权
标题翻译：使用列表解码校正错误码字中的错误
公开(公告)号：US08898539B2
公开(公告)日：2014-11-25
申请号：US13611158
申请日：2012-09-12
申请人： Yang Han , Shaohua Yang , Zongwang Li , Fan Zhang , Anatoli A. Bolotov , Mikhail I. Grinchuk , Paul G. Filseth , Lav D. Ivanovic
发明人： Yang Han , Shaohua Yang , Zongwang Li , Fan Zhang , Anatoli A. Bolotov , Mikhail I. Grinchuk , Paul G. Filseth , Lav D. Ivanovic
IPC分类号： H03M13/00
CPC分类号： H03M13/6337 , H03M13/09 , H03M13/1102 , H03M13/1128 , H03M13/152 , H03M13/2957 , H03M13/3707 , H03M13/3753 , H03M13/451
摘要： A receive path of a communications system comprises an error-correction decoder, an error-detection decoder, and a codeword adjuster. The error-correction decoder performs error-correction decoding on a received codeword to generate a valid codeword. The error-detection decoder performs error-detection decoding on the valid codeword to determine whether or not the valid codeword is the correct codeword that was transmitted. If the valid codeword is not the correct codeword, then the codeword adjuster generates an adjusted valid codeword by applying an error vector to the valid codeword. The error-detection decoder performs error-detection decoding on the adjusted valid codeword to determine whether or not the adjusted valid codeword is the correct codeword. When the error-correction decoder generates an incorrect valid codeword, adjusting the valid codeword enables the receive path to recover the correct codeword without retransmitting or re-detecting the codeword.
摘要翻译：通信系统的接收路径包括纠错解码器，错误检测解码器和码字调节器。误差校正解码器对接收的码字进行纠错解码，以生成有效的码字。错误检测解码器对有效码字执行错误检测解码，以确定有效码字是否是发送的正确码字。如果有效码字不是正确的码字，则码字调节器通过向有效码字应用误差向量来生成经调整的有效码字。错误检测解码器对经调整的有效码字执行错误检测解码，以确定调整后的有效码字是否为正确码字。当纠错解码器产生不正确的有效码字时，调整有效码字使得接收路径能够恢复正确的码字而不重传或重新检测码字。

8. 发明申请

US20130283114A1 Systems and Methods for Locating and Correcting Decoder Mis-Corrections 有权
标题翻译：用于定位和校正解码器误差校正的系统和方法
公开(公告)号：US20130283114A1
公开(公告)日：2013-10-24
申请号：US13450289
申请日：2012-04-18
申请人： Shaohua Yang , Yang Han , Chung-Li Wang , Mikhail I. Grinchuk , Anatoli A. Bolotov , Lav D. Ivanovic
发明人： Shaohua Yang , Yang Han , Chung-Li Wang , Mikhail I. Grinchuk , Anatoli A. Bolotov , Lav D. Ivanovic
IPC分类号： G06F11/07 , H03M13/05 , G06F11/10 , H03M13/09
CPC分类号： H03M13/00 , G11B20/1833 , G11B2020/1843 , G11B2020/185 , G11B2220/2516 , G11B2220/415 , H03M7/6005 , H03M13/093 , H03M13/1102 , H03M13/1108 , H03M13/1128 , H03M13/3723 , H03M13/3746 , H03M13/41 , H03M13/6511 , H03M13/6513
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, data processing systems are disclosed that include a data decoding circuit having a data decoder circuit, an element modification circuit, an element modification log, and a mis-correction detection circuit.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，公开了包括具有数据解码器电路，元件修改电路，元件修改日志和错误校正检测电路的数据解码电路的数据处理系统。

9. 发明授权

US08359479B2 High performance arithmetic logic unit (ALU) for cryptographic applications with built-in countermeasures against side channel attacks 有权
标题翻译：用于加密应用的高性能算术逻辑单元（ALU），具有针对侧面信道攻击的内置对策
公开(公告)号：US08359479B2
公开(公告)日：2013-01-22
申请号：US12218756
申请日：2008-07-17
申请人： Mikhail I. Grinchuk , Anatoli A. Bolotov , Lav D. Ivanovic , Paul G. Filseth
发明人： Mikhail I. Grinchuk , Anatoli A. Bolotov , Lav D. Ivanovic , Paul G. Filseth
IPC分类号： G06F12/14
CPC分类号： G06F7/723 , G06F2207/7223 , G06F2207/7266 , H04L9/002 , H04L9/0662
摘要： The present invention is a cryptoengine configured for providing countermeasures against attacks, including: an input/output (I/O) control unit, a memory, a controller, and an Arithmetic Logic Unit (ALU). The memory is communicatively coupled with the I/O control unit, receives inputs from the I/O control unit, and provides outputs to the I/O control unit based upon the received inputs. The controller is communicatively coupled with the I/O control unit for transmitting and receiving control signals. The ALU includes a plurality of storage components and computational components. The ALU is communicatively coupled with the controller and receives commands from/transmits status bits and flags to the controller. The ALU is further communicatively coupled with the memory and is configured for providing output signals to/receiving input signals from the memory. Further, the cryptoengine is configured for being communicatively coupled with a host computing device.
摘要翻译：本发明是一种配置用于提供针对攻击的对策的密码引擎，包括：输入/输出（I / O）控制单元，存储器，控制器和算术逻辑单元（ALU）。存储器与I / O控制单元通信地耦合，从I / O控制单元接收输入，并根据接收的输入向I / O控制单元提供输出。控制器与I / O控制单元通信耦合，用于发送和接收控制信号。 ALU包括多个存储组件和计算组件。 ALU与控制器通信耦合，并从控制器接收/发送状态位和标志的命令。 ALU进一步与存储器通信耦合，并且被配置为向存储器提供/接收输入信号的输出信号。此外，密码引擎被配置为与主机计算设备通信地耦合。

10. 发明授权

US08023644B2 Multimode block cipher architectures 有权
标题翻译：多模块分组密码体系结构
公开(公告)号：US08023644B2
公开(公告)日：2011-09-20
申请号：US11928628
申请日：2007-10-30
申请人： Anatoli A. Bolotov , Mikhail I. Grinchuk , Lav D. Ivanovic , Paul G. Filseth , Anton I. Sabev
发明人： Anatoli A. Bolotov , Mikhail I. Grinchuk , Lav D. Ivanovic , Paul G. Filseth , Anton I. Sabev
IPC分类号： H04L9/00
CPC分类号： H04L9/0637 , H04L2209/125
摘要： An architecture for a block cipher, where the architecture includes functional units that are logically reconfigurable so as to be able to both encrypt clear text into cipher text and decrypt cipher text into clear text using more than one block cipher mode based on at least one of advanced encryption standard and data encryption standard.
摘要翻译：一种用于块密码的架构，其中该架构包括在逻辑上可重新配置的功能单元，以便能够将明文加密为密文，并使用多于一个的块加密模式，将密文解密为明文，高级加密标准和数据加密标准。

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