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1. 发明授权

US06731554B1 2T2C signal margin test mode using resistive element 失效
标题翻译： 2T2C信号余量测试模式使用电阻元件
公开(公告)号：US06731554B1
公开(公告)日：2004-05-04
申请号：US10301546
申请日：2002-11-20
申请人： Michael Jacob , Joerg Wohlfahrt , Thomas Roehr , Nobert Rehm
发明人： Michael Jacob , Joerg Wohlfahrt , Thomas Roehr , Nobert Rehm
IPC分类号： G11C2900
CPC分类号： G11C29/50 , G11C11/22
摘要： The present invention provides a test mode section for facilitating a worst case product test sequence for signal margin to ensure full product functionality over the entire component lifetime taking all aging effects into account. A semiconductor memory test mode configuration includes a first capacitor for storing digital data connecting a cell plate line to a first bit line through a first select transistor. The first select transistor is activated through a connection to a word line. A second capacitor stores digital data and connects the cell plate line to a second bit line through a second select transistor. The second select transistor is activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines for measuring a differential read signal on the first and second bit lines A resistor is connected to one or both of the bit lines through transistors for adding or reducing the amount of charge on the first bit line when the third transistor is turned on to reduce the differential read signal.
摘要翻译：本发明提供了一种测试模式部分，用于促进针对信号余量的最坏情况产品测试序列，以确保在整个组件寿命期间的全部产品功能，同时考虑所有的老化效应。半导体存储器测试模式配置包括：第一电容器，用于存储通过第一选择晶体管将单元板线连接到第一位线的数字数据。第一个选择晶体管通过与字线的连接来激活。第二电容器存储数字数据，并通过第二选择晶体管将单元板线连接到第二位线。通过与字线的连接激活第二选择晶体管。读出放大器连接到第一和第二位线，用于测量第一和第二位线上的差分读取信号。电阻器通过晶体管连接到一个或两个位线，用于增加或减少第一和第二位线上的电荷量当第三晶体管导通时减小差分读取信号的位线。

2. 发明申请

US20050050261A1 High density flash memory with high speed cache data interface 审中-公开
标题翻译：高密度闪存与高速缓存数据接口
公开(公告)号：US20050050261A1
公开(公告)日：2005-03-03
申请号：US10650458
申请日：2003-08-27
申请人： Thomas Roehr , Michael Jacob , Nobert Rehm , Hans-Oliver Joachim
发明人： Thomas Roehr , Michael Jacob , Nobert Rehm , Hans-Oliver Joachim
IPC分类号： G06F12/08 , G11C8/12 , G11C16/10 , G06F12/00
CPC分类号： G11C8/12 , G06F12/0893 , G06F2212/2022 , G06F2212/2024 , G11C16/10 , G11C2207/2245
摘要： A data storage device comprises a controller, a FeRAM memory unit, and a flash memory unit having a much higher data storage capacity than the FeRAM memory unit. Initially, when data is received by the data storage device, the controller stores it in the FeRAM memory unit. This can be done very quickly, since FeRAM devices have a high write rate. Subsequently, the controller transfers the data to the flash memory unit. Thus, the data storage device combines the high storage rate ability of FeRAM devices and the high storage capacity of flash memory devices.
摘要翻译：数据存储装置包括控制器，FeRAM存储器单元和具有比FeRAM存储器单元高得多的数据存储容量的闪存单元。最初，当数据存储装置接收到数据时，控制器将其存储在FeRAM存储单元中。这可以非常快速地完成，因为FeRAM器件具有高写入速率。随后，控制器将数据传送到闪存单元。因此，数据存储设备结合了FeRAM器件的高存储容量和闪存器件的高存储容量。

3. 发明授权

US06876590B2 2T2C signal margin test mode using a defined charge exchange between BL and/BL 失效
标题翻译： 2T2C信号余量测试模式，使用BL和/ BL之间定义的电荷交换
公开(公告)号：US06876590B2
公开(公告)日：2005-04-05
申请号：US10301548
申请日：2002-11-20
申请人： Hans-Oliver Joachim , Michael Jacob , Nobert Rehm
发明人： Hans-Oliver Joachim , Michael Jacob , Nobert Rehm
IPC分类号： G11C29/50 , G11C29/00
CPC分类号： G11C29/50 , G11C11/22
摘要： The present invention provides a test mode section for facilitating a worst case product test sequence for signal margin to ensure full product functionality over the entire component lifetime taking all aging effects into account. A semiconductor memory test mode configuration includes a first capacitor for storing digital data and connecting a cell plate line to a first bit line through a first select transistor. The first select transistor activated through a connection to a word line. A second capacitor stores digital data and connects the cell plate line to a second bit line through a second select transistor. The second select transistor is activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines and measures a differential read signal on the first and second bit lines. A third transistor transfers charge between the first and second bit lines third to reduce the differential read signal.
摘要翻译：本发明提供了一种测试模式部分，用于促进用于信号余量的最坏情况产品测试序列，以确保整个组件寿命期间的全部产品功能，从而考虑所有老化效应。半导体存储器测试模式配置包括用于存储数字数据并通过第一选择晶体管将单元板线连接到第一位线的第一电容器。通过连接到字线而激活的第一选择晶体管。第二电容器存储数字数据，并通过第二选择晶体管将单元板线连接到第二位线。通过与字线的连接激活第二选择晶体管。读出放大器连接到第一和第二位线，并测量第一和第二位线上的差分读取信号。第三晶体管在第一和第二位线之间传输电荷，以减少差分读取信号。

4. 发明授权

US07092274B2 Ferroelectric memory device 有权
标题翻译：铁电存储器件
公开(公告)号：US07092274B2
公开(公告)日：2006-08-15
申请号：US10963589
申请日：2004-10-14
申请人： Katsuhiko Hoya , Daisaburo Takashima , Nobert Rehm
发明人： Katsuhiko Hoya , Daisaburo Takashima , Nobert Rehm
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A ferroelectric memory device includes a memory cell array having memory cells arranged in a matrix form. Each of the memory cells includes a cell transistor and a ferroelectric capacitor. It further includes a first dummy bit line arranged outside a bit line arranged on an end portion of the memory cell array and separated from the bit line arranged on the end portion of the memory cell array with an interval which is the same as a pitch between the bit lines in the memory cell array and having the same width as the bit line, and a first dummy memory cell connected to the first dummy bit line and having the same structure as the memory cell.
摘要翻译：铁电存储器件包括具有以矩阵形式布置的存储单元的存储单元阵列。每个存储单元包括单元晶体管和铁电电容器。其还包括布置在存储单元阵列的端部上的位线之外的第一虚位位线，并且以与间隔相等的间隔与存储单元阵列的端部分布的位线分开，存储单元阵列中的位线并且具有与位线相同的宽度，以及连接到第一虚拟位线并具有与存储单元相同结构的第一虚拟存储单元。

5. 发明授权

US06822891B1 Ferroelectric memory device 有权
标题翻译：铁电存储器件
公开(公告)号：US06822891B1
公开(公告)日：2004-11-23
申请号：US10461367
申请日：2003-06-16
申请人： Katsuhiko Hoya , Daisaburo Takashima , Nobert Rehm
发明人： Katsuhiko Hoya , Daisaburo Takashima , Nobert Rehm
IPC分类号： G11C700
CPC分类号： G11C11/22
摘要： A ferroelectric memory device includes a memory cell array having memory cells arranged in a matrix form. Each of the memory cells includes a cell transistor and a ferroelectric capacitor. It further includes a first dummy bit line arranged outside a bit line arranged on an end portion of the memory cell array and separated from the bit line arranged on the end portion of the memory cell array with an interval which is the same as a pitch between the bit lines in the memory cell array and having the same width as the bit line, and a first dummy memory cell connected to the first dummy bit line and having the same structure as the memory cell.
摘要翻译：铁电存储器件包括具有以矩阵形式布置的存储单元的存储单元阵列。每个存储单元包括单元晶体管和铁电电容器。其还包括布置在存储单元阵列的端部上的位线之外的第一虚位位线，并且以与间隔相等的间隔与存储单元阵列的端部分布的位线分开，存储单元阵列中的位线并且具有与位线相同的宽度，以及连接到第一虚拟位线并具有与存储单元相同结构的第一虚拟存储单元。

6. 发明申请

US20050047188A1 Ferroelectric memory device 有权
标题翻译：铁电存储器件
公开(公告)号：US20050047188A1
公开(公告)日：2005-03-03
申请号：US10963589
申请日：2004-10-14
申请人： Katsuhiko Hoya , Daisaburo Takashima , Nobert Rehm
发明人： Katsuhiko Hoya , Daisaburo Takashima , Nobert Rehm
IPC分类号： G11C7/00 , G11C11/08 , G11C11/22
CPC分类号： G11C11/22
摘要： A ferroelectric memory device includes a memory cell array having memory cells arranged in a matrix form. Each of the memory cells includes a cell transistor and a ferroelectric capacitor. It further includes a first dummy bit line arranged outside a bit line arranged on an end portion of the memory cell array and separated from the bit line arranged on the end portion of the memory cell array with an interval which is the same as a pitch between the bit lines in the memory cell array and having the same width as the bit line, and a first dummy memory cell connected to the first dummy bit line and having the same structure as the memory cell.
摘要翻译：铁电存储器件包括具有以矩阵形式布置的存储单元的存储单元阵列。每个存储单元包括单元晶体管和铁电电容器。其还包括布置在存储单元阵列的端部上的位线之外的第一虚位位线，并且以与间隔相等的间隔与存储单元阵列的端部分布的位线分开，存储单元阵列中的位线并且具有与位线相同的宽度，以及连接到第一虚拟位线并具有与存储单元相同结构的第一虚拟存储单元。

7. 发明授权

US07102908B2 Reliable ferro fuse cell 有权
标题翻译：可靠的铁熔丝电池
公开(公告)号：US07102908B2
公开(公告)日：2006-09-05
申请号：US10651753
申请日：2003-08-29
申请人： Roehr Thomas , Hans-Oliver Joachim , Nobert Rehm
发明人： Roehr Thomas , Hans-Oliver Joachim , Nobert Rehm
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： The present invention includes a ferro fuse cell comprising a ferroelectric storage capacitor electrically connected to a plate on one side and to a sense amplifier on the other side. A ferroelectric measurement capacitor is electrically connected between the ferroelectric storage capacitor and the sense amplifier.
摘要翻译：本发明包括一个铁熔体单元，其包括电连接到一侧的板和另一侧的读出放大器的铁电存储电容器。铁电测量电容器电连接在铁电存储电容器和读出放大器之间。

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