专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06724026B2 Memory architecture with memory cell groups 有权
标题翻译：内存架构与内存单元组
公开(公告)号：US06724026B2
公开(公告)日：2004-04-20
申请号：US10065123
申请日：2002-09-19
申请人： Michael Jacob , Andreas Hilliger , Thomas Roehr , Susumo Shuto , Toru Ozaki
发明人： Michael Jacob , Andreas Hilliger , Thomas Roehr , Susumo Shuto , Toru Ozaki
IPC分类号： H01L2976
CPC分类号： H01L27/11502 , G11C11/22 , H01L27/11507
摘要： An improved cell design for series memory architecture is disclosed. The improved cell design facilitates the formation of capacitors using a single etch process instead of two, as conventionally required. In one embodiment, each capacitor of a capacitor pair is provided with at least one plug contacting a common diffusion region of two adjacent cell transistors. In another embodiment, a large plug with sufficient overlap to the bottom electrodes of pair of capacitors is used.
摘要翻译：公开了用于串行存储器架构的改进的单元设计。改进的电池设计有助于使用单一蚀刻工艺形成电容器，而不是如常规要求的那样。在一个实施例中，电容器对的每个电容器设置有接触两个相邻单元晶体管的公共扩散区域的至少一个插头。在另一个实施例中，使用与一对电容器的底部电极具有足够重叠的大插头。

2. 发明授权

US06731554B1 2T2C signal margin test mode using resistive element 失效
标题翻译： 2T2C信号余量测试模式使用电阻元件
公开(公告)号：US06731554B1
公开(公告)日：2004-05-04
申请号：US10301546
申请日：2002-11-20
申请人： Michael Jacob , Joerg Wohlfahrt , Thomas Roehr , Nobert Rehm
发明人： Michael Jacob , Joerg Wohlfahrt , Thomas Roehr , Nobert Rehm
IPC分类号： G11C2900
CPC分类号： G11C29/50 , G11C11/22
摘要： The present invention provides a test mode section for facilitating a worst case product test sequence for signal margin to ensure full product functionality over the entire component lifetime taking all aging effects into account. A semiconductor memory test mode configuration includes a first capacitor for storing digital data connecting a cell plate line to a first bit line through a first select transistor. The first select transistor is activated through a connection to a word line. A second capacitor stores digital data and connects the cell plate line to a second bit line through a second select transistor. The second select transistor is activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines for measuring a differential read signal on the first and second bit lines A resistor is connected to one or both of the bit lines through transistors for adding or reducing the amount of charge on the first bit line when the third transistor is turned on to reduce the differential read signal.
摘要翻译：本发明提供了一种测试模式部分，用于促进针对信号余量的最坏情况产品测试序列，以确保在整个组件寿命期间的全部产品功能，同时考虑所有的老化效应。半导体存储器测试模式配置包括：第一电容器，用于存储通过第一选择晶体管将单元板线连接到第一位线的数字数据。第一个选择晶体管通过与字线的连接来激活。第二电容器存储数字数据，并通过第二选择晶体管将单元板线连接到第二位线。通过与字线的连接激活第二选择晶体管。读出放大器连接到第一和第二位线，用于测量第一和第二位线上的差分读取信号。电阻器通过晶体管连接到一个或两个位线，用于增加或减少第一和第二位线上的电荷量当第三晶体管导通时减小差分读取信号的位线。

3. 发明授权

US06950328B2 Imprint suppression circuit scheme 失效
标题翻译：压印抑制电路方案
公开(公告)号：US06950328B2
公开(公告)日：2005-09-27
申请号：US10734439
申请日：2003-12-11
申请人： Thomas Roehr , Michael Jacob
发明人： Thomas Roehr , Michael Jacob
IPC分类号： G11C7/02 , G11C7/08 , G11C7/18 , G11C8/12 , G11C11/22 , H01L27/105
CPC分类号： G11C11/22
摘要： A ferroelectric memory array includes a plurality of memory pages each formed of a plurality of ferroelectric memory cells. The ferroelectric memory cells are supplied by common word lines. Status memory cells are connected to each of the plurality of memory pages, each status memory cell stores the status of the memory page to which it is connected. A plurality of sense amplifiers each receives inputs from a pair of bit lines. Each of the bit lines receives inputs from the ferroelectric memory cells of a plurality of the memory pages. The sense amplifiers write back data into the memory cells and status cells in reversed states following read operations.
摘要翻译：铁电存储器阵列包括由多个铁电存储器单元形成的多个存储器页。铁电存储单元由公用字线提供。状态存储器单元连接到多个存储器页中的每一个，每个状态存储单元存储与其连接的存储器页的状态。多个读出放大器各自接收来自一对位线的输入。每个位线接收来自多个存储器页的铁电存储单元的输入。在读操作之后，感测放大器将数据写入存储单元和状态单元。

4. 发明申请

US20050128779A1 Imprint suppression circuit scheme 失效
公开(公告)号：US20050128779A1
公开(公告)日：2005-06-16
申请号：US10734439
申请日：2003-12-11
申请人： Thomas Roehr , Michael Jacob
发明人： Thomas Roehr , Michael Jacob
IPC分类号： G11C7/02 , G11C7/08 , G11C7/18 , G11C8/12 , G11C11/22 , H01L27/105
CPC分类号： G11C11/22
摘要： A ferroelectric memory array includes a plurality of memory pages each formed of a plurality of ferroelectric memory cells. The ferroelectric memory cells are supplied by common word lines. Status memory cells are connected to each of the plurality of memory pages, each status memory cell stores the status of the memory page to which it is connected. A plurality of sense amplifiers each receives inputs from a pair of bit lines. Each of the bit lines receives inputs from the ferroelectric memory cells of a plurality of the memory pages. The sense amplifiers write back data into the memory cells and status cells in reversed states following read operations.

5. 发明授权

US06639824B1 Memory architecture 有权
标题翻译：内存架构
公开(公告)号：US06639824B1
公开(公告)日：2003-10-28
申请号：US10065126
申请日：2002-09-19
申请人： Joerg Wohlfahrt , Norbert Rehm , Michael Jacob , Thomas Roehr
发明人： Joerg Wohlfahrt , Norbert Rehm , Michael Jacob , Thomas Roehr
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： An IC with memory cells arranged in groups is described. The memory cells, for example, are ferroelectric memory cells. The IC includes a variable voltage generator (VVG) for generating an output voltage having a different voltage level depending on a location of an addressed memory cell within the memory group is provided. By providing different voltage levels for reads and/or writes, signal loss caused by capacitances which is dependent on the location of the memory cell within the group can be avoided. This improves read and/or write operations in series memory architectures.
摘要翻译：描述了具有分组排列的存储单元的IC。存储单元例如是铁电存储单元。该IC包括一个可变电压发生器（VVG），用于根据存储器组内寻址的存储器单元的位置产生具有不同电压电平的输出电压。通过为读取和/或写入提供不同的电压电平，可以避免由取决于组内的存储器单元的位置的电容引起的信号损失。这改善了串行存储器架构中的读取和/或写入操作。

6. 发明申请

US20050050261A1 High density flash memory with high speed cache data interface 审中-公开
标题翻译：高密度闪存与高速缓存数据接口
公开(公告)号：US20050050261A1
公开(公告)日：2005-03-03
申请号：US10650458
申请日：2003-08-27
申请人： Thomas Roehr , Michael Jacob , Nobert Rehm , Hans-Oliver Joachim
发明人： Thomas Roehr , Michael Jacob , Nobert Rehm , Hans-Oliver Joachim
IPC分类号： G06F12/08 , G11C8/12 , G11C16/10 , G06F12/00
CPC分类号： G11C8/12 , G06F12/0893 , G06F2212/2022 , G06F2212/2024 , G11C16/10 , G11C2207/2245
摘要： A data storage device comprises a controller, a FeRAM memory unit, and a flash memory unit having a much higher data storage capacity than the FeRAM memory unit. Initially, when data is received by the data storage device, the controller stores it in the FeRAM memory unit. This can be done very quickly, since FeRAM devices have a high write rate. Subsequently, the controller transfers the data to the flash memory unit. Thus, the data storage device combines the high storage rate ability of FeRAM devices and the high storage capacity of flash memory devices.
摘要翻译：数据存储装置包括控制器，FeRAM存储器单元和具有比FeRAM存储器单元高得多的数据存储容量的闪存单元。最初，当数据存储装置接收到数据时，控制器将其存储在FeRAM存储单元中。这可以非常快速地完成，因为FeRAM器件具有高写入速率。随后，控制器将数据传送到闪存单元。因此，数据存储设备结合了FeRAM器件的高存储容量和闪存器件的高存储容量。

7. 发明授权

US07187602B2 Reducing memory failures in integrated circuits 有权
标题翻译：减少集成电路中的内存故障
公开(公告)号：US07187602B2
公开(公告)日：2007-03-06
申请号：US10250211
申请日：2003-06-13
申请人： Joerg Wohlfahrt , Thomas Roehr , Michael Jacob
发明人： Joerg Wohlfahrt , Thomas Roehr , Michael Jacob
IPC分类号： G11C29/42 , G11C29/04 , G11C29/24 , G11C11/22
CPC分类号： G06F11/1008 , G11C11/22 , G11C29/72
摘要： Memory reliability is improved by using redundancy to repair errors detected by ECC. In one embodiment, redundancy repairs errors which cannot be corrected by ECC. The redundancy can employ the use of electronic fuses, enabling repairs after an IC containing the memory is packaged. Redundancy can also be performed prior to packaging of the IC.
摘要翻译：通过使用冗余来修复ECC检测到的错误，可以提高内存的可靠性。在一个实施例中，冗余修复由ECC无法纠正的错误。冗余可以使用电子保险丝，在包含存储器的IC封装后进行维修。还可以在封装IC之前执行冗余。

8. 发明授权

US06920059B2 Reducing effects of noise coupling in integrated circuits with memory arrays 失效
标题翻译：降低与存储器阵列集成电路中噪声耦合的影响
公开(公告)号：US06920059B2
公开(公告)日：2005-07-19
申请号：US10065921
申请日：2002-11-29
申请人： Michael Jacob , Thomas Roehr , Norbert Rehm , Daisaburo Takashima
发明人： Michael Jacob , Thomas Roehr , Norbert Rehm , Daisaburo Takashima
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A method for reducing noise coupling in a memory array is disclosed. The memory array includes a plurality memory cells interconnected by wordlines, bitlines, and platelines. The memory cells are arranged in columns having first and second bitlines coupled to a sense amplifier. During a memory access, at least adjacent bitlines pairs are not activated. The selected bitline pair or pairs are provided with a plateline pulse.
摘要翻译：公开了一种减少存储器阵列中的噪声耦合的方法。存储器阵列包括通过字线，位线和平行线互连的多个存储器单元。存储单元被布置成具有耦合到读出放大器的第一和第二位线的列。在存储器访问期间，至少相邻的位线对不被激活。选定的位线对或对配有一条平行线脉冲。

9. 发明授权

US06885597B2 Sensing test circuit 失效
标题翻译：感应测试电路
公开(公告)号：US06885597B2
公开(公告)日：2005-04-26
申请号：US10065011
申请日：2002-09-10
申请人： Thomas Roehr , Hans-Oliver Joachim , Michael Jacob , Joerg Wohlfahrt , Takashima Daisaburo
发明人： Thomas Roehr , Hans-Oliver Joachim , Michael Jacob , Joerg Wohlfahrt , Takashima Daisaburo
IPC分类号： G11C29/50 , G11C29/00
CPC分类号： G11C29/50 , G11C11/22 , G11C2029/1204 , G11C2029/5004
摘要： A test circuit for testing differential read signals during a memory access is disclosed. The test circuit is coupled to a pair of bit lines. During a read access, a selected memory cell produces a differential read signal on the bit lines. When the test circuit is activated, the magnitude of the differential read signal is varied. This enables easy testing of read signal margins in, for example, memory ICs.
摘要翻译：公开了一种用于在存储器访问期间测试差分读取信号的测试电路。测试电路耦合到一对位线。在读访问期间，所选存储单元在位线上产生差分读信号。当测试电路被激活时，差分读取信号的幅度是变化的。这使得能够容易地测试例如存储器IC中的读取信号余量。

10. 发明申请

US20050063213A1 Signal margin test mode for FeRAM with ferroelectric reference capacitor 审中-公开
标题翻译：具有铁电参考电容的FeRAM的信号余量测试模式
公开(公告)号：US20050063213A1
公开(公告)日：2005-03-24
申请号：US10665402
申请日：2003-09-18
申请人： Michael Jacob , Thomas Roehr , Hans-Oliver Joachim
发明人： Michael Jacob , Thomas Roehr , Hans-Oliver Joachim
IPC分类号： G11C29/50 , G11C11/22
CPC分类号： G11C29/50 , G11C11/22 , G11C2029/5002 , G11C2029/5004
摘要： The present invention provides a semiconductor memory test mode configuration. A first capacitor stores digital data and connects a cell plate line to a first bit-line through a first select transistor. The first select transistor is activated through a connection to a word line. At least one reference capacitor provides a reference voltage to a reference bit-line. A sense amplifier is connected to the first and reference bit-lines and measures a differential read signal on the first and reference bit-lines. A charge path reduces the differential read signal to determine the signal margin of the semiconductor memory.
摘要翻译：本发明提供半导体存储器测试模式配置。第一电容器存储数字数据，并且通过第一选择晶体管将单元板线连接到第一位线。第一个选择晶体管通过与字线的连接来激活。至少一个参考电容器为参考位线提供参考电压。读出放大器连接到第一和参考位线，并测量第一和参考位线上的差分读取信号。充电路径减小差分读取信号以确定半导体存储器的信号余量。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式