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1. 发明授权

US06724026B2 Memory architecture with memory cell groups 有权
标题翻译：内存架构与内存单元组
公开(公告)号：US06724026B2
公开(公告)日：2004-04-20
申请号：US10065123
申请日：2002-09-19
申请人： Michael Jacob , Andreas Hilliger , Thomas Roehr , Susumo Shuto , Toru Ozaki
发明人： Michael Jacob , Andreas Hilliger , Thomas Roehr , Susumo Shuto , Toru Ozaki
IPC分类号： H01L2976
CPC分类号： H01L27/11502 , G11C11/22 , H01L27/11507
摘要： An improved cell design for series memory architecture is disclosed. The improved cell design facilitates the formation of capacitors using a single etch process instead of two, as conventionally required. In one embodiment, each capacitor of a capacitor pair is provided with at least one plug contacting a common diffusion region of two adjacent cell transistors. In another embodiment, a large plug with sufficient overlap to the bottom electrodes of pair of capacitors is used.
摘要翻译：公开了用于串行存储器架构的改进的单元设计。改进的电池设计有助于使用单一蚀刻工艺形成电容器，而不是如常规要求的那样。在一个实施例中，电容器对的每个电容器设置有接触两个相邻单元晶体管的公共扩散区域的至少一个插头。在另一个实施例中，使用与一对电容器的底部电极具有足够重叠的大插头。

2. 发明授权

US07071506B2 Device for inhibiting hydrogen damage in ferroelectric capacitor devices 失效
标题翻译：用于抑制铁电电容器件中的氢损伤的装置
公开(公告)号：US07071506B2
公开(公告)日：2006-07-04
申请号：US10655757
申请日：2003-09-05
申请人： Bum-Ki Moon , Karl Hornik , Haoren Zhuang , Ulrich Egger , Jenny Lian , Andreas Hilliger
发明人： Bum-Ki Moon , Karl Hornik , Haoren Zhuang , Ulrich Egger , Jenny Lian , Andreas Hilliger
IPC分类号： H01L29/76
CPC分类号： H01L28/57 , H01L27/0805 , H01L27/11507
摘要： A ferroelectric capacitor device comprises a substrate, a contact plug passing through the substrate, a first electrode formed on the substrate, the first electrode being electrically connected to said plug, a ferroelectric layer formed on the first electrode, a second electrode formed on the ferroelectric layer, one or more first encapsulation layers on the second electrode, the encapsulation layers extending over the device, and one or more hydrogen storage material layers on the encapsulation layers. One or more second encapsulation layers may be formed on the one or more hydrogen storage material layers.
摘要翻译：铁电电容器装置包括基板，穿过基板的接触插塞，形成在基板上的第一电极，第一电极电连接到所述插头，形成在第一电极上的铁电层，形成在铁电体上的第二电极层，在第二电极上的一个或多个第一封装层，在器件上延伸的封装层以及封装层上的一个或多个储氢材料层。一个或多个第二封装层可以形成在一个或多个储氢材料层上。

3. 发明授权

US06858442B2 Ferroelectric memory integrated circuit with improved reliability 失效
标题翻译：铁电存储器集成电路具有改进的可靠性
公开(公告)号：US06858442B2
公开(公告)日：2005-02-22
申请号：US10248861
申请日：2003-02-25
申请人： Andreas Hilliger , Uwe Wellhausen
发明人： Andreas Hilliger , Uwe Wellhausen
IPC分类号： G11C20060101 , G11C11/22 , H01L21/00 , H01L21/02 , H01L21/768 , H01L21/8242 , H01L21/8246 , H01L27/108 , H01L27/115 , H01L21/8142
CPC分类号： H01L28/55 , G11C11/22 , H01L21/76829 , H01L21/76831 , H01L21/76832 , H01L27/11502 , H01L28/65 , H01L28/75
摘要： A memory cell having capacitor with top and bottom electrodes with a dielectric layer between is described. The bottom electrode is coupled to a first diffusion region of a transistor by a bottom electrode plug. A dielectric layer covers the capacitor. Above the dielectric layer is a first barrier layer. A via is created in the dielectric layer in which a plug is formed to couple to the second diffusion region. The via comprises substantially vertical sidewalls. A second barrier layer lines the sidewalls of the via. A conductive material is then deposited on the substrate, filling the via to form the plug. By providing the first and second barrier layers, the diffusion of hydrogen which can adversely impact the capacitor is reduced, thereby improving the reliability.
摘要翻译：描述了具有电介质层的具有电介质层的电容器的存储单元。底部电极通过底部电极插塞耦合到晶体管的第一扩散区域。电介质层覆盖电容器。电介质层之上是第一阻挡层。在其中形成有插塞以耦合到第二扩散区域的电介质层中形成通孔。通孔包括基本垂直的侧壁。第二阻挡层对通孔的侧壁进行排列。然后将导电材料沉积在衬底上，填充通孔以形成插头。通过设置第一和第二阻挡层，可以减小可能不利地影响电容器的氢的扩散，从而提高可靠性。

4. 发明申请

US20050020054A1 Formation of a contact in a device, and the device including the contact 有权
标题翻译：在设备中形成联系人，以及包括联系人的设备
公开(公告)号：US20050020054A1
公开(公告)日：2005-01-27
申请号：US10625483
申请日：2003-07-22
申请人： Andreas Hilliger , Stefan Gernhardt , Uwe Wellhausen , Karl Hornik
发明人： Andreas Hilliger , Stefan Gernhardt , Uwe Wellhausen , Karl Hornik
IPC分类号： H01L21/02 , H01L21/768 , H01L23/522 , H01L27/115 , H01L21/4763
CPC分类号： H01L23/5226 , H01L21/76802 , H01L21/76831 , H01L27/11502 , H01L28/57 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a contact to an underlayer of a device includes the steps of forming a contact hole, forming a contact hole barrier layer of a barrier material in the contact hole of the device, etching the contact hole barrier layer on the bottom surface of the contact hole, depositing a liner material in the contact hole, and filling the contact hole with a conductive material. A device such as a semiconductor, passive device, capacitor or FeRAM is formed in accordance with the method. The portions of the contact hole barrier layer on the side walls of the contact hole inhibit lateral diffusion of hydrogen and/or oxygen. The contact hole barrier layer can be performed after a wet etch process to fill voids in an existing barrier layer caused by that process, or prior to the wet etch process to prevent damage to the existing barrier layer.
摘要翻译：与器件的底层形成接触的方法包括以下步骤：形成接触孔，在器件的接触孔中形成阻挡材料的接触孔阻挡层，蚀刻位于接触孔底面的接触孔阻挡层接触孔，将衬垫材料沉积在接触孔中，并用导电材料填充接触孔。根据该方法形成诸如半导体，无源器件，电容器或FeRAM的器件。接触孔的侧壁上的接触孔阻挡层的部分阻止氢和/或氧的横向扩散。接触孔阻挡层可以在湿蚀刻工艺之后进行，以填充由该工艺引起的现有阻挡层中的空隙，或者在湿蚀刻工艺之前，以防止对现有阻挡层的损坏。

5. 发明授权

US06614642B1 Capacitor over plug structure 有权
标题翻译：电容器插头结构
公开(公告)号：US06614642B1
公开(公告)日：2003-09-02
申请号：US10065122
申请日：2002-09-19
申请人： Bum-ki Moon , Moto Yabuki , Gerhard Beitel , Nicolas Nagel , Andreas Hilliger , Takamichi Tsuchiya
发明人： Bum-ki Moon , Moto Yabuki , Gerhard Beitel , Nicolas Nagel , Andreas Hilliger , Takamichi Tsuchiya
IPC分类号： H01G4228
CPC分类号： H01L28/75 , H01L21/28568 , H01L28/60 , H01L28/90
摘要： A capacitor over plug (COP) structure is disclosed. The COP avoids the step which is created in conventional COP structures, which adversely impacts the properties of the capacitor. In one embodiment, the step is avoided by providing a plug having upper and lower portions. The upper portion, which is coupled to the bottom electrode of the capacitor, has substantially the same surface area as the bottom electrode. A barrier layer can be provided between the plug and bottom electrode to avoid oxidation of the plug material.
摘要翻译：公开了一种电容器插头（COP）结构。 COP避免了常规COP结构中产生的步骤，这对电容器的性能产生不利影响。在一个实施例中，通过提供具有上部和下部的插塞来避免该步骤。耦合到电容器的底部电极的上部具有与底部电极基本相同的表面积。可以在塞子和底部电极之间提供阻挡层以避免塞子材料的氧化。

6. 发明授权

US06611449B1 Contact for memory cells 有权
标题翻译：存储单元的联系
公开(公告)号：US06611449B1
公开(公告)日：2003-08-26
申请号：US10065166
申请日：2002-09-24
申请人： Andreas Hilliger
发明人： Andreas Hilliger
IPC分类号： G11C1122
CPC分类号： H01L27/11502 , G11C11/22 , H01L27/11507
摘要： A memory cell which provides a diffusion path for hydrogen to the transistor is disclosed. The diffusion path is provided by forming a contact in which the upper section overlaps the lower section, thus creating a gap that serve as a hydrogen diffusion path. The hydrogen diffusion path is necessary for annealing the damage to the gate oxide.
摘要翻译：公开了一种向晶体管提供氢的扩散路径的存储单元。通过形成上部与下部重叠的接触来提供扩散路径，从而产生用作氢扩散路径的间隙。氢扩散路径对退火对栅极氧化物的损伤是必需的。

7. 发明授权

US07101785B2 Formation of a contact in a device, and the device including the contact 有权
标题翻译：在设备中形成联系人，以及包括联系人的设备
公开(公告)号：US07101785B2
公开(公告)日：2006-09-05
申请号：US10625483
申请日：2003-07-22
申请人： Andreas Hilliger , Stefan Gernhardt , Uwe Wellhausen , Karl Hornik
发明人： Andreas Hilliger , Stefan Gernhardt , Uwe Wellhausen , Karl Hornik
IPC分类号： H01L21/4763
CPC分类号： H01L23/5226 , H01L21/76802 , H01L21/76831 , H01L27/11502 , H01L28/57 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a contact to an underlayer of a device includes the steps of forming a contact hole, forming a contact hole barrier layer of a barrier material in the contact hole of the device, etching the contact hole barrier layer on the bottom surface of the contact hole, depositing a liner material in the contact hole, and filling the contact hole with a conductive material. A device such as a semiconductor, passive device, capacitor or FeRAM is formed in accordance with the method. The portions of the contact hole barrier layer on the side walls of the contact hole inhibit lateral diffusion of hydrogen and/or oxygen. The contact hole barrier layer can be performed after a wet etch process to fill voids in an existing barrier layer caused by that process, or prior to the wet etch process to prevent damage to the existing barrier layer.
摘要翻译：与器件的底层形成接触的方法包括以下步骤：形成接触孔，在器件的接触孔中形成阻挡材料的接触孔阻挡层，蚀刻位于接触孔底面的接触孔阻挡层接触孔，将衬垫材料沉积在接触孔中，并用导电材料填充接触孔。根据该方法形成诸如半导体，无源器件，电容器或FeRAM的器件。接触孔的侧壁上的接触孔阻挡层的部分阻止氢和/或氧的横向扩散。接触孔阻挡层可以在湿蚀刻工艺之后进行，以填充由该工艺引起的现有阻挡层中的空隙，或者在湿蚀刻工艺之前，以防止对现有阻挡层的损坏。

8. 发明授权

US07042705B2 Sidewall structure and method of fabrication for reducing oxygen diffusion to contact plugs during CW hole reactive ion etch processing 失效
标题翻译：在CW孔反应离子蚀刻处理期间用于减少氧扩散到接触塞的侧壁结构和制造方法
公开(公告)号：US07042705B2
公开(公告)日：2006-05-09
申请号：US10356690
申请日：2003-01-30
申请人： Haoren Zhuang , Ulrich Egger , Kazuhiro Tomioka , Jingyu Lian , Nicolas Nagel , Andreas Hilliger , Gerhard Beitel
发明人： Haoren Zhuang , Ulrich Egger , Kazuhiro Tomioka , Jingyu Lian , Nicolas Nagel , Andreas Hilliger , Gerhard Beitel
IPC分类号： H01G4/10
CPC分类号： H01L28/55 , H01L21/31116 , H01L28/57
摘要： The present invention provides a sidewall oxygen diffusion barrier and a method for fabricating the sidewall oxygen diffusion barrier that reduces the diffusion of oxygen into contact plugs during a CW hole reactive ion etch of a ferroelectric capacitor of an FeRAM device. In one embodiment the sidewall barrier is formed from a substrate fence. In another embodiment, the sidewall barrier is formed by etching back an oxygen barrier.
摘要翻译：本发明提供一种侧壁氧扩散阻挡层和制造侧壁氧扩散阻挡层的方法，该方法在FeRAM器件的铁电电容器的CW孔反应离子蚀刻期间减少氧气扩散到接触塞中。在一个实施例中，侧壁屏障由衬底围栏形成。在另一个实施例中，通过蚀刻回氧屏障来形成侧壁屏障。

9. 发明授权

US07042037B1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07042037B1
公开(公告)日：2006-05-09
申请号：US10986060
申请日：2004-11-12
申请人： Hiroshi Itokawa , Koji Yamakawa , Tohru Ozaki , Yoshinori Kumura , Takamichi Tsuchiya , Nicolas Nagel , Bum-Ki Moon , Andreas Hilliger
发明人： Hiroshi Itokawa , Koji Yamakawa , Tohru Ozaki , Yoshinori Kumura , Takamichi Tsuchiya , Nicolas Nagel , Bum-Ki Moon , Andreas Hilliger
IPC分类号： H01L31/062
CPC分类号： H01L28/55 , G11C11/22 , H01L27/11502 , H01L27/11507 , H01L28/65
摘要： Disclosed is a semiconductor device comprising a semiconductor substrate, a capacitor provided above the semiconductor substrate and including a bottom electrode, a top electrode, and a dielectric film provided between the bottom electrode and the top electrode, the bottom electrode comprising a first conductive film containing iridium, a second conductive film provided between the dielectric film and the first conductive film and formed of a noble metal film, a third conductive film provided between the dielectric film and the second conductive film and formed of a metal oxide film having a perovskite structure, and a diffusion prevention film provided between the first conductive film and the second conductive film and including at least one of a metal film and a metal oxide film, the diffusion prevention film preventing diffusion of iridium contained in the first conductive film.
摘要翻译：公开了一种半导体器件，包括半导体衬底，设置在半导体衬底上方并包括底电极，顶电极和设置在底电极和顶电极之间的电介质膜的电容器，底电极包括含有铱，设置在电介质膜和第一导电膜之间并由贵金属膜形成的第二导电膜，设置在电介质膜和第二导电膜之间并由具有钙钛矿结构的金属氧化物膜形成的第三导电膜，以及设置在所述第一导电膜和所述第二导电膜之间并且包括金属膜和金属氧化物膜中的至少一种的防扩散膜，所述扩散防止膜防止包含在所述第一导电膜中的铱的扩散。

10. 发明授权

US07009230B2 Barrier stack with improved barrier properties 失效
标题翻译：阻隔层具有改善的阻隔性能
公开(公告)号：US07009230B2
公开(公告)日：2006-03-07
申请号：US10604323
申请日：2003-07-10
申请人： Bum Ki Moon , Gerhard Beitel , Nicolas Nagel , Andreas Hilliger , Koji Yamakawa , Keitaro Imai
发明人： Bum Ki Moon , Gerhard Beitel , Nicolas Nagel , Andreas Hilliger , Koji Yamakawa , Keitaro Imai
IPC分类号： H01L29/76
CPC分类号： H01L27/11502 , H01L21/28568 , H01L27/11507 , H01L28/55 , H01L28/75
摘要： An improved barrier stack for inhibiting diffusion of atoms or molecules, such as O2 is disclosed. The barrier stack is particularly useful in capacitor over plug structures to prevent plug oxidation which can adversely impact the reliability of the structures. The barrier stack includes first and second barrier layers. In one embodiment, the first barrier layer comprises first and second sub-barrier layers having mismatched grain boundaries. The sub-barrier layers are selected from, for example, Ir, Ru, Pd, Rh, or alloys thereof. By providing mismatched grain boundaries, the interface of the sub-barrier layers block the diffusion path of oxygen. To further enhance the barrier properties, the first barrier layer is passivated with O2 using, for example, a rapid thermal oxidation. The RTO forms a thin oxide layer on the surface of the first barrier layer. The oxide layer can advantageously promote mismatching of the grain boundaries of the first and second sub-barrier layer. The second barrier layer comprises a conductive oxide.
摘要翻译：公开了用于抑制原子或分子扩散的改进的阻挡层，例如O 2。势垒堆叠在电容器超过插塞结构中特别有用，以防止插塞氧化，这可能不利地影响结构的可靠性。阻挡层包括第一和第二阻挡层。在一个实施例中，第一阻挡层包括具有失配的晶界的第一和第二子阻挡层。亚阻挡层选自例如Ir，Ru，Pd，Rh或其合金。通过提供错配的晶界，子阻挡层的界面阻挡氧的扩散路径。为了进一步增强阻挡性能，使用例如快速热氧化，第一阻挡层用O 2 2钝化。 RTO在第一阻挡层的表面上形成薄的氧化物层。氧化物层可以有利地促进第一和第二子阻挡层的晶界的失配。第二阻挡层包括导电氧化物。

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