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    • 1. 发明授权
    • Line unit interface circuit
    • 线路单元接口电路
    • US4993019A
    • 1991-02-12
    • US451436
    • 1989-12-15
    • Gary B. ColeMichael J. GingellJoseph E. SutherlandPaul M. Matsumura
    • Gary B. ColeMichael J. GingellJoseph E. SutherlandPaul M. Matsumura
    • H04Q11/04
    • H04Q11/04
    • A line unit interface circuit used on line units in a line shelf of a digital loop carrier provides all of the logic necessary to access two subscriber lines to a line unit interface bus connected to common equipment within the line shelf. Information received from the common equipment includes signaling data, configuration data and provisioning data, which is reconfigured and processed by the line unit interface circuit for controlling the subscriber line channels. Configuration data from the common equipment is decoded to assign time slots on the line unit interface bus to the various channels serviced by the line shelf and to further provide for a timing offset between the transmit and receive strobes provided to each subscriber line circuit. A flywheel circuit is used to prevent erroneous time slot assignment in the event of noise or interference on the line unit interface bus.
    • 在数字环路载波的线路架中的线路单元上使用的线路单元接口电路提供了将两条用户线路连接到线路架内的公共设备的线路单元接口总线所需的所有逻辑。 从公共设备接收的信息包括由线路单元接口电路重新配置和处理的用于控制用户线路信道的信令数据,配置数据和供应数据。 解码来自公共设备的配置数据,以将线路单元接口总线上的时隙分配给由线路架服务的各种通道,并进一步提供提供给每个用户线电路的发射和接收选通之间的定时偏移。 飞轮电路用于在线路单元接口总线上发生噪声或干扰的情况下防止错误的时隙分配。
    • 7. 发明授权
    • Elastic storage and synchronization control apparatus for use in a
telephone switching system
    • 用于电话交换系统的弹性存储和同步控制装置
    • US4323790A
    • 1982-04-06
    • US156713
    • 1980-06-05
    • Stephen C. DunningJoseph E. Sutherland
    • Stephen C. DunningJoseph E. Sutherland
    • H04J3/07
    • H04J3/073
    • An elastic storage circuit employs a first in/first out (FIFO) memory which stores data contained in a serial stream in a plurality of locations, each of which is associated with a unique address. The storage locations operate to store both the data and the address. A word address counter generates a five bit address code to accompany the data bits as stored in the FIFO. If a chronic increase or decrease in the frequency rate of the data occurs, the FIFO will overflow or underflow. This condition is detected by suitable detectors which create an alarm to completely reset the entire contents of the memory and to refill a portion of the memory over a given interval sufficient to permit the system to recover from the slip in the data rate and to thereafter synchronously read the data together with the address identification from the FIFO.
    • 弹性存储电路采用将多个位置中的串行流中包含的数据存储在第一输入/输出(FIFO)存储器中,每个位置与唯一地址相关联。 存储位置操作以存储数据和地址。 一个字地址计数器产生一个五位地址码,以便存储在FIFO中的数据位。 如果发生数据频率的慢慢增加或减少,则FIFO会溢出或下溢。 该条件由合适的检测器检测,该检测器产生报警以完全重置存储器的全部内容,并且在给定的间隔内重新填充存储器的一部分,足以允许系统以数据速率从滑移中恢复,然后同步 从FIFO读取数据和地址标识。