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1. 发明授权

US5548711A Method and apparatus for fault tolerant fast writes through buffer dumping 失效
标题翻译：通过缓冲倾倒进行容错快速写入的方法和装置
公开(公告)号：US5548711A
公开(公告)日：1996-08-20
申请号：US363655
申请日：1994-12-22
申请人： William A. Brant , Gary Neben , Michael E. Nielson , David C. Stallmo
发明人： William A. Brant , Gary Neben , Michael E. Nielson , David C. Stallmo
IPC分类号： G06F11/10 , G06F11/14 , G06F11/20 , G06F12/08 , G06F11/00
CPC分类号： G06F11/1666 , G06F11/1076 , G06F11/1435 , G06F11/1658 , G06F11/2017 , G06F11/2092 , G06F11/2094 , G06F11/1441 , G06F11/20 , G06F11/2087 , G06F12/0866 , G06F2211/1019 , G06F2211/1059
摘要： An array controller including a DATA-RAM and a SHADOW-RAM. Both the DATA-RAM and the SHADOW-RAM are coupled to a first and second memory interface. Each memory interface has the ability to independently communicate the contents of the SHADOW-RAM over a controller-controller data link to at least one other similar array controller. The memory interface also interfaces the DATA-RAM and the SHADOW-RAM to a CPU, the data storage units of the RAID system, and the controller processor. Write data received from the CPU is stored in the two independent memories in order to ensure that pending Write data (i.e., Write data that has not yet been written to the RAID system, including any copyback cache device) will not be lost. In addition, the two memory interfaces provide redundant access routes which allow Write data to be retrieved by another array controller if the controller processor fails. A backup power source is provided to ensure that power will be available to at least one of the two memories such that the data that has been received within the controller will always be accessible. Accordingly, since the data will be accessible, even if of a failure of any single component or power source occurs, the controller may acknowledge the write operation requested by the CPU as soon as data is successfully written to both the DATA-RAM and the SHADOW-RAM.
摘要翻译：阵列控制器，包括DATA-RAM和SHADOW-RAM。 DATA-RAM和SHADOW-RAM都耦合到第一和第二存储器接口。每个存储器接口能够通过控制器 - 控制器数据链路独立地将SHADOW-RAM的内容传送到至少一个其他类似的阵列控制器。存储器接口还将DATA-RAM和SHADOW-RAM连接到CPU，RAID系统的数据存储单元和控制器处理器。从CPU接收的写入数据被存储在两个独立的存储器中，以便确保不会丢失未决的写入数据（即尚未写入RAID系统的写入数据，包括任何拷贝缓存设备）。此外，两个存储器接口提供冗余访问路由，如果控制器处理器发生故障，允许由另一个阵列控制器检索写入数据。提供备用电源以确保对两个存储器中的至少一个存储器可用的功率使得在控制器内已经接收到的数据将始终是可访问的。因此，由于数据可访问，即使发生任何单个组件或电源发生故障，一旦数据成功写入DATA-RAM和SHADOW，控制器就可以确认CPU请求的写操作 -随机存取存储器。

2. 发明授权

US5905854A Fault tolerant memory system 失效
标题翻译：容错存储系统
公开(公告)号：US5905854A
公开(公告)日：1999-05-18
申请号：US721522
申请日：1996-09-26
申请人： Michael E. Nielson , William A. Brant , Gary Neben
发明人： Michael E. Nielson , William A. Brant , Gary Neben
IPC分类号： G06F11/10 , G06F11/16 , G06F11/20 , G11C29/00 , G06F11/00
CPC分类号： G06F11/167 , G06F11/1076 , G06F11/2087 , G11C29/74 , G06F11/10 , G06F2211/1009
摘要： A fault tolerant memory system is disclosed which includes a main memory device, storing data and an associated error detecting code, and a shadow memory device, storing data corresponding to the data stored in the main memory. A multiplexer, selectively couples data from either the main memory device or the shadow memory device to an output terminal in response to a control signal. A controller reads the data and associated error detecting code from the main memory device and the corresponding data from the shadow memory device, and generates the multiplexer control signal such that the multiplexer couples data from the shadow memory device to the output terminal if the data from the main memory device is not the same as the data from the shadow memory device and the error detecting code indicate an error in the data from the main memory device, and otherwise couples the data from the main memory device Lo the output terminal.
摘要翻译：公开了一种容错存储器系统，其包括主存储器件，存储数据和相关联的错误检测代码，以及存储与存储在主存储器中的数据相对应的数据的影子存储器设备。复用器响应于控制信号选择性地将数据从主存储器件或影子存储器件耦合到输出端子。控制器从主存储器件读取数据和相关的错误检测代码以及来自影子存储器件的相应数据，并产生多路复用器控制信号，使得多路复用器将数据从影子存储器件耦合到输出端，如果来自主存储器件与来自影子存储器件的数据不同，并且错误检测代码指示来自主存储器件的数据中的错误，否则将来自主存储器件Lo的数据耦合到输出端子。

3. 发明授权

US5619642A Fault tolerant memory system which utilizes data from a shadow memory device upon the detection of erroneous data in a main memory device 失效
标题翻译：容错存储器系统，其在检测到主存储器件中的错误数据时利用来自影子存储器件的数据
公开(公告)号：US5619642A
公开(公告)日：1997-04-08
申请号：US363132
申请日：1994-12-23
申请人： Michael E. Nielson , William A. Brant , Gary Neben
发明人： Michael E. Nielson , William A. Brant , Gary Neben
IPC分类号： G06F11/10 , G06F11/16 , G06F11/20 , G11C29/00 , G06F11/00
CPC分类号： G06F11/167 , G06F11/1076 , G06F11/2087 , G11C29/74 , G06F11/10 , G06F2211/1009
摘要： A fault tolerant memory system is disclosed which includes a main memory device, storing data and an associated error detecting code, and a shadow memory device, storing data corresponding to the data stored in the main memory. A multiplexer, selectively couples data from either the main memory device or the shadow memory device to an output terminal in response to a control signal. A controller reads the data and associated error detecting code from the main memory device and the corresponding data from the shadow memory device, and generates the multiplexer control signal such that the multiplexer couples data from the shadow memory device to the output terminal if the data from the main memory device is not the same as the data from the shadow memory device and the error detecting code indicate an error in the data from the main memory device, and otherwise couples the data from the main memory device to the output terminal.
摘要翻译：公开了一种容错存储器系统，其包括主存储器件，存储数据和相关联的错误检测代码，以及存储与存储在主存储器中的数据相对应的数据的影子存储器设备。复用器响应于控制信号选择性地将数据从主存储器件或影子存储器件耦合到输出端子。控制器从主存储器件读取数据和相关的错误检测代码以及来自影子存储器件的相应数据，并产生多路复用器控制信号，使得多路复用器将数据从影子存储器件耦合到输出端，如果来自主存储器件与来自影子存储器件的数据不同，并且错误检测代码指示来自主存储器件的数据中的错误，否则将数据从主存储器件耦合到输出端子。

4. 发明授权

US5799200A Power failure responsive apparatus and method having a shadow dram, a flash ROM, an auxiliary battery, and a controller 失效
标题翻译：具有阴影的电源故障响应装置和方法，闪存ROM，辅助电池和控制器
公开(公告)号：US5799200A
公开(公告)日：1998-08-25
申请号：US536519
申请日：1995-09-28
申请人： William A. Brant , Michael E. Nielson , Edde Tin-Shek Tang
发明人： William A. Brant , Michael E. Nielson , Edde Tin-Shek Tang
IPC分类号： G06F1/30 , G06F11/14 , G06F1/00
CPC分类号： G06F1/30 , G06F11/1441
摘要： Data in a system having dynamic random access memories (DRAM's) is preserved despite loss of the primary source of electrical power to that system. A Flash RAM and a small auxiliary power source are employed by a controller independent of the system to transfer the DRAM contents to the Flash RAM immediately upon loss of primary system power. The data is also automatically returned to the DRAM after return of primary power with special data signals or sequences being utilized in a multiple controller environment so as to award the complete data recovery function to the first controller to demand attention.
摘要翻译：尽管丢失了该系统的主要电源，仍保留了具有动态随机存取存储器（DRAM）的系统中的数据。闪存RAM和小型辅助电源被独立于系统的控制器采用，以在主系统电源丢失时立即将DRAM内容传送到闪存RAM。在多次控制器环境中使用特殊数据信号或序列返回主电源之后，数据也自动返回到DRAM，以便将完整的数据恢复功能授予第一控制器以要求注意。

5. 发明授权

US5469566A Flexible parity generation circuit for intermittently generating a parity for a plurality of data channels in a redundant array of storage units 失效
标题翻译：灵活的奇偶生成电路，用于在存储单元的冗余阵列中间歇地产生用于多个数据信道的奇偶校验
公开(公告)号：US5469566A
公开(公告)日：1995-11-21
申请号：US402963
申请日：1995-03-10
申请人： Gerald L. Hohenstein , Michael E. Nielson , Tin S. Tang , Richard D. Carmichael , William A. Brant
发明人： Gerald L. Hohenstein , Michael E. Nielson , Tin S. Tang , Richard D. Carmichael , William A. Brant
IPC分类号： G06F11/10 , G11B20/18 , H03M13/00 , G06F11/00
CPC分类号： G06F11/1076 , G11B20/1833 , G06F2211/1054
摘要： A redundant array computer system having a high-speed CPU bus and lower-speed I/O buses, in which parity blocks are generated for a plurality of data blocks from multiple CPU bus logical channels in a randomly-interleaved manner to provide enhanced I/O transfer rates. For example, such a system may have two channels for processing two sets of data. The parity generation technique employs a switching circuit to switch channels on the CPU bus between the first set and the second set, generating parity information that can be transferred independently over two I/O buses. The parity generation technique achieves an effective I/O bus transfer rate more closely matched to the speed of the CPU bus. The invention shares a single XOR gate and related support circuitry between multiple logical channels by providing a configurable electronic memory, thus achieving economies in implementation. For certain system applications, it may be desirable to utilize the RAM as a large, unified FIFO. Thus, the system can be adapted to generate parity information for very large blocks of data in a single channel.
摘要翻译：具有高速CPU总线和低速I / O总线的冗余阵列计算机系统，其中以随机交错方式从多个CPU总线逻辑信道为多个数据块生成奇偶校验块，以提供增强的I / O转移率。例如，这样的系统可以具有用于处理两组数据的两个通道。奇偶生成技术采用切换电路来切换第一组和第二组之间的CPU总线上的通道，产生可以通过两个I / O总线独立传输的奇偶校验信息。奇偶生成技术实现了与CPU总线速度更接近的有效I / O总线传输速率。本发明通过提供可配置的电子存储器来共享多个逻辑信道之间的单个XOR门和相关的支持电路，从而实现实现的经济性。对于某些系统应用，可能希望将RAM用作大型统一的FIFO。因此，该系统可以适于在单个信道中为非常大的数据块生成奇偶校验信息。

6. 发明授权

US5831393A Flexible parity generation circuit 失效
标题翻译：灵活的奇偶生成电路
公开(公告)号：US5831393A
公开(公告)日：1998-11-03
申请号：US832050
申请日：1997-04-02
申请人： Gerald Lee Hohenstein , Michael E. Nielson , Tin S. Tang , Richard D. Carmichael , William A. Brant
发明人： Gerald Lee Hohenstein , Michael E. Nielson , Tin S. Tang , Richard D. Carmichael , William A. Brant
IPC分类号： G06F11/10 , G11B20/18 , G06F11/00
CPC分类号： G06F11/1076 , G11B20/1833 , G06F2211/1054
摘要： A redundant array computer system having a high-speed CPU bus and lower-speed I/O buses, in which parity blocks are generated for a plurality of data blocks from multiple CPU bus logical channels in a randomly-interleaved manner to provide enhanced I/O transfer rates. For example, such a system may have two channels for processing two sets of data. The parity generation technique employs switching means to switch channels on the CPU bus between the first set and the second set, generating parity information that can be transferred independently over two I/O buses. The parity generation technique achieves an effective I/O bus transfer rate more closely matched to the speed of the CPU bus. The invention shares a single XOR gate and related support circuitry between multiple logical channels by providing a configurable electronic memory, thus achieving economies in implementation. For certain system applications, it may be desirable to utilize the RAM as a large, unified FIFO. Thus, the system can be adapted to generate parity information for very large blocks of data in a single channel.
摘要翻译：具有高速CPU总线和低速I / O总线的冗余阵列计算机系统，其中以随机交错方式从多个CPU总线逻辑信道为多个数据块生成奇偶校验块，以提供增强的I / O转移率。例如，这样的系统可以具有用于处理两组数据的两个通道。奇偶产生技术采用切换装置来切换第一组和第二组之间的CPU总线上的通道，产生可以通过两个I / O总线独立传输的奇偶校验信息。奇偶生成技术实现了与CPU总线速度更接近的有效I / O总线传输速率。本发明通过提供可配置的电子存储器来共享多个逻辑信道之间的单个XOR门和相关的支持电路，从而实现实现的经济性。对于某些系统应用，可能希望将RAM用作大型统一的FIFO。因此，该系统可以适于在单个信道中为非常大的数据块生成奇偶校验信息。

7. 发明授权

US5675726A Flexible parity generation circuit 失效
标题翻译：灵活的奇偶生成电路
公开(公告)号：US5675726A
公开(公告)日：1997-10-07
申请号：US555331
申请日：1995-11-08
申请人： Gerald Lee Hohenstein , Michael E. Nielson , Tin S. Tang , Richard D. Carmichael , William A. Brant
发明人： Gerald Lee Hohenstein , Michael E. Nielson , Tin S. Tang , Richard D. Carmichael , William A. Brant
IPC分类号： G06F11/10 , G11B20/18 , G06F11/00
CPC分类号： G06F11/1076 , G11B20/1833 , G06F2211/1054
摘要： A redundant array computer system having a high-speed CPU bus and lower-speed I/O buses, in which parity blocks are generated for a plurality of data blocks from multiple CPU bus logical channels in a randomly-interleaved manner to provide enhanced I/O transfer rates. For example, such a system may have two channels for processing two sets of data. The parity generation technique employs switching means to switch channels on the CPU bus between the first set and the second set, generating parity information that can be transferred independently over two I/O buses. The parity generation technique achieves an effective I/O bus transfer rate more closely matched to the speed of the CPU bus. The invention shares a single XOR gate and related support circuitry between multiple logical channels by providing a configurable electronic memory, thus achieving economies in implementation. For certain system applications, it may be desirable to utilize the RAM as a large, unified FIFO. Thus, the system can be adapted to generate parity information for very large blocks of data in a single channel.
摘要翻译：具有高速CPU总线和低速I / O总线的冗余阵列计算机系统，其中以随机交错方式从多个CPU总线逻辑信道为多个数据块生成奇偶校验块，以提供增强的I / O转移率。例如，这样的系统可以具有用于处理两组数据的两个通道。奇偶产生技术采用切换装置来切换第一组和第二组之间的CPU总线上的通道，产生可以通过两个I / O总线独立传输的奇偶校验信息。奇偶生成技术实现了与CPU总线速度更接近的有效I / O总线传输速率。本发明通过提供可配置的电子存储器来共享多个逻辑信道之间的单个XOR门和相关的支持电路，从而实现实现的经济性。对于某些系统应用，可能希望将RAM用作大型统一的FIFO。因此，该系统可以适于在单个信道中为非常大的数据块生成奇偶校验信息。

8. 发明授权

US06760807B2 System, apparatus and method providing adaptive write policy for disk array controllers 有权
标题翻译：为磁盘阵列控制器提供自适应写入策略的系统，设备和方法
公开(公告)号：US06760807B2
公开(公告)日：2004-07-06
申请号：US09993235
申请日：2001-11-14
申请人： William A. Brant , William G. Deitz , Michael E. Nielson , Joseph G. Skazinski
发明人： William A. Brant , William G. Deitz , Michael E. Nielson , Joseph G. Skazinski
IPC分类号： G06F1200
CPC分类号： G06F11/2089 , G06F3/0601 , G06F11/2097 , G06F2003/0697
摘要： Adaptive write policy for handling host write commands to write-back system drives in a dual active controller environment. Method for adaptive write policy in data storage system, where data storage system includes host system connected to primary controller and alternate controller. Controllers are coupled to system drive that includes one or more disk storage devices. Primary is connected to first memory and alternate is connected to second memory. Primary and alternate manage data storage system in dual-active configuration. Primary controller receives host write command from host system and write data request includes host write data. When system drive is configured with write-back policy, primary determines whether host write command encompasses an entire RAID stripe, and if so, primary processes host write command in accordance with write-through policy. Otherwise, primary processes command in accordance with write-back policy. Reduces amount of host write data that has to be mirrored to alternate controller.
摘要翻译：用于处理主机写命令以在双主动控制器环境中回写系统驱动器的自适应写策略。数据存储系统中自适应写入策略的方法，其中数据存储系统包括连接到主控制器和备用控制器的主机系统。控制器耦合到包括一个或多个磁盘存储设备的系统驱动器。主要连接到第一个存储器，备用连接到第二个存储器。主要和备用管理数据存储系统双重配置。主控制器从主机系统接收主机写命令，写数据请求包括主机写数据。当系统驱动器配置有回写策略时，主要确定主机写入命令是否包含整个RAID条带，如果是，则根据直写策略主进程主机写入命令。否则，主进程按照回写策略进行命令。减少必须镜像到备用控制器的主机写入数据量。

9. 发明授权

US06438647B1 Method and apparatus for providing battery-backed immediate write back cache for an array of disk drives in a computer system 有权
标题翻译：用于为计算机系统中的磁盘驱动器阵列提供电池支持的即时回写高速缓存的方法和装置
公开(公告)号：US06438647B1
公开(公告)日：2002-08-20
申请号：US09602808
申请日：2000-06-23
申请人： Michael E. Nielson , Thomas E. Richardson
发明人： Michael E. Nielson , Thomas E. Richardson
IPC分类号： G06F118
CPC分类号： G06F11/2097 , G06F11/2092 , G06F12/0804 , G06F12/0866
摘要： The present invention provides a method and apparatus for providing battery-backed immediate write back cache for an array of disk drives in a computer system. Cooperation between a new replacement controller and a survivor controller is enabled so that write back cache operation can start immediately, and not be dependant on the battery condition in the replacement controller. Protection of the data through a single point of failure is maintained. When a controller fails, a replacement controller is installed and battery state information is exchanged. If any battery backup meets a predetermined threshold, all of the controllers run in the write back cache mode. However, if not one of the battery backups meets a predetermined threshold, all of the controllers run in the write through cache mode. Thus, the system does not need to wait for a replacement controller's battery backup to be reconditioned before the higher speed write back cache is used.
摘要翻译：本发明提供一种用于为计算机系统中的磁盘驱动器阵列提供电池支持的立即回写高速缓存的方法和装置。启用新的更换控制器和幸存者控制器之间的合作，使得回写高速缓存操作可以立即启动，而不是取决于更换控制器中的电池状况。维护通过单点故障保护数据。当控制器发生故障时，安装更换控制器并交换电池状态信息。如果任何电池备份满足预定阈值，则所有控制器都以回写高速缓存模式运行。然而，如果不是其中一个电池备份满足预定阈值，则所有控制器都以写入高速缓存模式运行。因此，在使用更高速度的回写高速缓存之前，系统不需要等待替换控制器的电池备份来重新调整。

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