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1. 发明申请

US20060200723A1 Method and apparatus for implementing enhanced vertical ECC storage in a dynamic random access memory 失效
标题翻译：用于在动态随机存取存储器中实现增强的垂直ECC存储的方法和装置
公开(公告)号：US20060200723A1
公开(公告)日：2006-09-07
申请号：US11071086
申请日：2005-03-03
申请人： Michael Carnevale , Steven Herndon , Daniel Moertl
发明人： Michael Carnevale , Steven Herndon , Daniel Moertl
IPC分类号： H03M13/00
CPC分类号： G06F11/1044
摘要： A method and apparatus are provided for implementing enhanced vertical ECC storage in a dynamic random access memory. A dynamic random access memory (DRAM) is split into a plurality of groups. Each group resides inside a DRAM row address strobe (RAS) page so that multiple locations inside a group can be accessed without incurring an additional RAS access penalty. Each group is logically split into a plurality of segments for storing data with at least one segment for storing ECC for the data segments. For a write operation, data are written in a data segment and then ECC for the data are written in an ECC segment. For a read operation, ECC are read from an ECC segment, then data are read from the data segment.
摘要翻译：提供了一种用于在动态随机存取存储器中实现增强的垂直ECC存储的方法和装置。动态随机存取存储器（DRAM）被分成多个组。每个组都驻留在DRAM行地址选通（RAS）页面中，从而可以访问组内的多个位置，而不会引起额外的RAS访问损失。每个组在逻辑上分成多个段，用于存储具有用于存储数据段的ECC的至少一个段的数据。对于写入操作，将数据写入数据段，然后将ECC用于数据写入ECC段。对于读取操作，从ECC段读取ECC，然后从数据段读取数据。

2. 发明申请

US20050083956A1 Buffer management for a target channel adapter 失效
标题翻译：目标通道适配器的缓冲区管理
公开(公告)号：US20050083956A1
公开(公告)日：2005-04-21
申请号：US10688220
申请日：2003-10-16
申请人： Michael Carnevale , Daniel Moertl , Timothy Schimke
发明人： Michael Carnevale , Daniel Moertl , Timothy Schimke
IPC分类号： H04L12/56 , H04L12/54
CPC分类号： H04L49/901 , H04L49/90 , H04L49/9047
摘要： A method, apparatus, system, and signal-bearing medium that in an embodiment determine whether a current number of buffers allocated to a queue pair is less than a maximum number of buffers for the queue pair, decide whether a current number of buffers allocated to an operation type is less than a maximum number of buffers for the operation, and allocate a buffer to the queue pair if the queue pair requests the buffer for an operation having the operation type and the determining and the deciding are true. In this way, too much buffer space is prevented from being assigned to particular operation and to a particular queue pair.
摘要翻译：一种方法，装置，系统和信号承载介质，其在一个实施例中确定分配给队列对的当前数量的缓冲器是否小于队列对的最大缓冲器数量，决定当前分配给操作类型小于操作缓冲区的最大数量，如果队列对请求具有操作类型的操作的缓冲区以及确定和判定为真，则将缓冲区分配给队列对。以这种方式，防止将太多的缓冲区空间分配给特定的操作和特定的队列对。

3. 发明申请

US20060161706A1 Storage controller and methods for using the same 失效
公开(公告)号：US20060161706A1
公开(公告)日：2006-07-20
申请号：US11038711
申请日：2005-01-20
申请人： Venkidesh Iyer , Daniel Moertl
发明人： Venkidesh Iyer , Daniel Moertl
IPC分类号： G06F13/14
CPC分类号： G06F13/28 , G06F13/1689
摘要： In a first aspect, a first method is provided for processing a request. The first method includes the steps of (1) receiving a request in first logic of a controller from a device master; (2) issuing a response to the device master to reissue the request at a later time; (3) notifying second logic of the controller of the request; (4) determining at least one of whether the request is valid and enough buffers are available to complete the request; (5) programming a filtering pipe; and (6) responding to the first logic based on at least one of whether the request is valid and enough buffers are available to complete the request such that the first logic may employ the filtering pipe to complete the request. The first logic operates in a first clock domain and second logic operates in a second clock domain. Numerous other aspects are provided.

4. 发明申请

US20080052423A1 STORAGE CONTROLLER AND METHODS FOR USING THE SAME 失效
标题翻译：存储控制器及其使用方法
公开(公告)号：US20080052423A1
公开(公告)日：2008-02-28
申请号：US11931640
申请日：2007-10-31
申请人： VENKIDESH IYER , Daniel Moertl
发明人： VENKIDESH IYER , Daniel Moertl
IPC分类号： G06F3/00
CPC分类号： G06F13/28 , G06F13/1689
摘要： In a first aspect, a first method is provided for processing a request. The first method includes the steps of (1) receiving a request in first logic of a controller from a device master; (2) issuing a response to the device master to reissue the request at a later time; (3) notifying second logic of the controller of the request; (4) determining at least one of whether the request is valid and enough buffers are available to complete the request; (5) programming a filtering pipe; and (6) responding to the first logic based on at least one of whether the request is valid and enough buffers are available to complete the request such that the first logic may employ the filtering pipe to complete the request. The first logic operates in a first clock domain and second logic operates in a second clock domain. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了一种处理请求的第一种方法。第一种方法包括以下步骤：（1）从设备主机接收控制器的第一逻辑中的请求; （2）向设备主人发出响应，以便稍后重新发出请求; （3）通知控制器的请求的第二逻辑; （4）确定所述请求是否有效和足够的缓冲区是否可用于完成请求中的至少一个; （5）对过滤管进行编程; 以及（6）基于所述请求是否有效并且足够的缓冲器是否可用于完成请求中的至少一个来响应第一逻辑，使得第一逻辑可以使用过滤管来完成请求。第一逻辑在第一时钟域中操作，第二逻辑在第二时钟域中操作。提供了许多其他方面。

5. 发明申请

US20050160215A1 Flow through asynchronous elastic FIFO apparatus and method for implementing multi-engine parsing and authentication 审中-公开
标题翻译：流过异步弹性FIFO装置和实现多引擎解析和认证的方法
公开(公告)号：US20050160215A1
公开(公告)日：2005-07-21
申请号：US10760446
申请日：2004-01-20
申请人： Daniel Moertl , Dennis Reetz , Donald Ziebarth
发明人： Daniel Moertl , Dennis Reetz , Donald Ziebarth
IPC分类号： G06F5/14 , G11C5/00
CPC分类号： G06F5/14 , G06F2205/102
摘要： A flow through asynchronous elastic first-in, first-out (FIFO) apparatus and method are provided for implementing multi-engine parsing and authentication. A FIFO random access memory (RAM) has a data input for receiving data and control information and a data output for outputting the data and control information. The FIFO RAM includes a plurality of locations for storing a plurality of words, each word including a set number of bits. Write clocked logic is provided for loading the data and control information to the FIFO RAM at a first clock frequency. Asynchronous read clocked logic is provided for outputting the data and control information from the FIFO RAM at a second clock frequency. The first clock frequency of the write clocked logic and the second clock frequency of the asynchronous read clocked logic and a data width of the FIFO RAM are selectively provided for outputting the data and control information from the FIFO RAM with no back pressure.
摘要翻译：提供了通过异步弹性先进先出（FIFO）装置和方法的流程，用于实现多引擎解析和认证。 FIFO随机存取存储器（RAM）具有用于接收数据和控制信息的数据输入和用于输出数据和控制信息的数据输出。 FIFO RAM包括用于存储多个单词的多个位置，每个单词包括设定位数。提供写时钟逻辑用于以第一时钟频率将数据和控制信息加载到FIFO RAM。提供异步读时钟逻辑，用于以第二时钟频率从FIFO RAM输出数据和控制信息。选择性地提供写时钟逻辑的第一时钟频率和异步读时钟逻辑的第二时钟频率以及FIFO RAM的数据宽度，用于从没有背压的FIFO RAM输出数据和控制信息。

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