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1. 发明授权

US5548560A Synchronous static random access memory having asynchronous test mode 失效
标题翻译：具有异步测试模式的同步静态随机存取存储器
公开(公告)号：US5548560A
公开(公告)日：1996-08-20
申请号：US423822
申请日：1995-04-19
申请人： Michael C. Stephens, Jr. , Ajit K. Medhekar , Chitranjan N. Reddy
发明人： Michael C. Stephens, Jr. , Ajit K. Medhekar , Chitranjan N. Reddy
IPC分类号： G11C7/22 , G11C8/18 , G11C8/00
CPC分类号： G11C7/22 , G11C8/18
摘要： A burst mode static random access memory (SRAM) (10) is disclosed that includes an address transition detect signal (ATD) generating circuit (14) that provides either an asynchronous ATD signal (a-ATD) or a synchronous ATD signal (s-ATD) depending upon the logic state of a mode signal (ATM). A rising edge of the a-ATD signal is generated by a change in address. A falling edge is generated after a predetermined time period according an a-ATD circuit (60) within the ATD generating circuit (14). A falling edge of the s-ATD signal is generated by a rising edge of an internal synchronous clock pulse (CLAT). The rising edge of the s-ATD signal is generated when data are sensed on data lines (40) by an end-of-cycle circuit (20). If ATM is high, the a-ATD signal is used for timing on the SRAM (10). If ATM is low, timing is determined according to the s-ATD signal. An ATD control circuit (16) is provided to generate I/O control signals in response to the ATD signal (either s-ATD or a-ATD). On a rising edge of the ATD signal the I/O control signals place the SRAM (10) in a precharge/equalization state wherein I/O lines (24, 32, 40) are equalized and sensing circuits (28, 34) are disabled. On a falling edge of the ATD signal, the SRAM (10) is placed in a read/write mode wherein the I/O lines (24, 32, 40) are ready to sense read data or be driven by written data, and sensing circuits (28, 34) are enabled for a read operation, or alternatively disabled for a write operation.
摘要翻译：公开了一种突发模式静态随机存取存储器（SRAM）（10），其包括地址转换检测信号（ATD）产生电路（14），其提供异步ATD信号（a-ATD）或同步ATD信号（s- ATD），取决于模式信号（ATM）的逻辑状态。 a-ATD信号的上升沿由地址变化产生。根据ATD生成电路（14）内的a-ATD电路（60），在预定时间段之后产生下降沿。 s-ATD信号的下降沿由内部同步时钟脉冲（CLAT）的上升沿产生。当通过循环周期电路（20）在数据线（40）上检测数据时，产生s-ATD信号的上升沿。如果ATM为高电平，则将a-ATD信号用于SRAM（10）上的定时。如果ATM低，则根据s-ATD信号确定定时。提供ATD控制电路（16）以响应于ATD信号（s-ATD或a-ATD）产生I / O控制信号。在ATD信号的上升沿，I / O控制信号将SRAM（10）置于预充电/均衡状态，其中I / O线（24,32,40）被均衡，并且感测电路（28,34）被禁用。在ATD信号的下降沿，SRAM（10）被置于读/写模式，其中I / O线（24,32,40）准备好读取数据或由写入数据驱动，并且感测电路（28,34）被启用用于读取操作，或者替代地禁用写入操作。

2. 发明授权

US5550783A Phase shift correction circuit for monolithic random access memory 失效
标题翻译：单片随机存取存储器的相移校正电路
公开(公告)号：US5550783A
公开(公告)日：1996-08-27
申请号：US424820
申请日：1995-04-19
申请人： Michael C. Stephens, Jr. , Ajit K. Medhekar
发明人： Michael C. Stephens, Jr. , Ajit K. Medhekar
IPC分类号： G11C7/22 , G11C8/00
CPC分类号： G11C7/225 , G11C7/22
摘要： A synchronous burst SRAM (110) is disclosed that includes a clock circuit (112) having a phase correction subcircuit (134) and a clock routing subcircuit (132). The clock routing subcircuit (132) provides an internal clock signal to at least one clocked circuit. The phase correction subcircuit (134) is a modified phase locked loop that includes a phase comparator (138) that receives an external clock signal and a delayed internal clock signal. In response to the signals, the phase comparator (138) provides a phase error signal to a charge pump (140) which is coupled to a loop filter (142) to provide an error voltage. The error voltage is coupled to a VCO (144) which provides the internal clock signal as an output. The internal clock signal is coupled to the input of the phase comparator (138) by a feedback circuit which generates the delayed internal clock signal for the phase comparator (138). The feedback circuit can include a number of delay elements (146) to simulate the clock delay inherent in the clock routing subcircuit (132) so that the resulting internal clock signal is phase shifted to compensate for delays caused by the clock routing subcircuit (132).
摘要翻译：公开了一种同步突发SRAM（110），其包括具有相位校正子电路（134）和时钟路由子电路（132）的时钟电路（112）。时钟路由分支电路（132）向至少一个时钟电路提供内部时钟信号。相位校正子电路（134）是修改的锁相环，其包括接收外部时钟信号和延迟的内部时钟信号的相位比较器（138）。响应于信号，相位比较器（138）向电荷泵（140）提供相位误差信号，电荷泵（140）耦合到环路滤波器（142）以提供误差电压。误差电压耦合到提供内部时钟信号作为输出的VCO（144）。内部时钟信号通过产生相位比较器（138）的延迟的内部时钟信号的反馈电路耦合到相位比较器（138）的输入端。反馈电路可以包括多个延迟元件（146），以模拟时钟路由子电路（132）中固有的时钟延迟，使得所得到的内部时钟信号相移以补偿由时钟路由子电路（132）引起的延迟，。

3. 发明授权

US5550500A Timing delay modulation scheme for integrated circuits 失效
标题翻译：集成电路定时延时调制方案
公开(公告)号：US5550500A
公开(公告)日：1996-08-27
申请号：US493901
申请日：1995-06-23
申请人： Michael C. Stephens, Jr. , Ajit K. Medhekar
发明人： Michael C. Stephens, Jr. , Ajit K. Medhekar
IPC分类号： H03K5/13 , H03K5/153
CPC分类号： H03K5/131 , H03K5/133
摘要： A timing delay modulation scheme for integrated circuits (10) is disclosed. A super voltage is applied to existing bond pads (30) and detected by super voltage detect circuits (34) which generate a number of logic input signals (22) to a logic unit (18). In response, the logic unit (18) provides a number of control signals (24) which are coupled to timing adjust circuits (20). In the preferred embodiment, in response to its respective control signals, each timing adjust circuit (20) pushes-out or pulls-in, a separate internal timing signal (S0-S3) of the integrated circuit. The super voltage detect circuit (34) includes an adjustable effective super voltage level, and is capable of being disabled. Further, the timing adjustment provided by each timing adjust circuit (20) can be altered.
摘要翻译：公开了一种用于集成电路（10）的定时延迟调制方案。超电压被施加到现有的接合焊盘（30）上，并由产生多个逻辑输入信号（22）的逻辑单元（18）的超电压检测电路（34）检测。作为响应，逻辑单元（18）提供耦合到定时调节电路（20）的多个控制信号（24）。在优选实施例中，响应于其各自的控制信号，每个定时调整电路（20）将集成电路的单独的内部定时信号（S0-S3）推出或拉入。超级电压检测电路（34）包括可调节的有效超级电平，并且能够被禁用。此外，可以改变由每个定时调整电路（20）提供的定时调整。

4. 发明授权

US5377146A Hierarchical redundancy scheme for high density monolithic memories 失效
标题翻译：高密度单片存储器的分层冗余方案
公开(公告)号：US5377146A
公开(公告)日：1994-12-27
申请号：US96732
申请日：1993-07-23
申请人： Chitranjan N. Reddy , Ajit K. Medhekar
发明人： Chitranjan N. Reddy , Ajit K. Medhekar
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/81 , G11C29/72
摘要： Hierarchical redundancy is implemented in a monolithic memory by providing standard row and column redundancy augmented by redundant blocks, each having its own internal row and block redundancy. The efficiency of the redundant blocks is further enhanced by subdividing the redundant blocks into individually replaceable segments of rows or columns. A test and repair algorithm utilizing the hierarchical redundancy scheme is also provided.
摘要翻译：通过提供由冗余块增加的标准行和列冗余，每个都具有自己的内部行和块冗余，在单片存储器中实现分层冗余。通过将冗余块细分为行或列的可单独替换的段来进一步增强冗余块的效率。还提供了利用分级冗余方案的测试和修复算法。

5. 发明授权

US6081440A Ternary content addressable memory (CAM) having fast insertion and deletion of data values 有权
标题翻译：具有快速插入和删除数据值的三元内容可寻址存储器（CAM）
公开(公告)号：US6081440A
公开(公告)日：2000-06-27
申请号：US186562
申请日：1998-11-05
申请人： James G. Washburn , Jayan Ramankutty , Ajit K. Medhekar
发明人： James G. Washburn , Jayan Ramankutty , Ajit K. Medhekar
IPC分类号： G11C15/00
CPC分类号： G11C15/00
摘要： A ternary content addressable memory (CAM) (800) having a massive, parallel shift capability is disclosed. The CAM (800) includes an array of CAM cells (802(1,1) to 802(1,4)), each of which includes a data value register (804(1,1) to 804(1,4)) and a mask value register (806(1,1) to 806(1,4)). To enable parallel shifting between a CAM cell in one row with a corresponding CAM cell in a higher row, each data value register (804(1,1) 804(1,4)) and mask value register (806(1,1) to 806(1,4)) includes an upper data input (UD) coupled the output of a CAM cell in the higher row. To enable parallel shifting between a CAM cell in one row with a corresponding CAM cell in a lower row, each data value register (804(1,1) 804(1,4)) and mask value register (806(1,1) to 806(1,4)) includes a lower data input (LD) coupled the output of a CAM cell in the lower row.
摘要翻译：公开了具有巨大的并行移位能力的三元内容可寻址存储器（CAM）（800）。 CAM（800）包括CAM单元阵列（802（1,1）至802（1,4）），其中每一个包括数据值寄存器（804（1,1）至804（1,4））和掩模值寄存器（806（1,1）〜806（1,4））。为了使一行中的CAM单元与较高行中的相应CAM单元之间的平行移位，每个数据值寄存器（804（1,1）804（1,4））和掩码值寄存器（806（1,1）至806（1,4））包括耦合在较高行中的CAM单元的输出的上部数据输入（UD）。为了使一行中的CAM单元与下行中的相应CAM单元之间的平行移位，每个数据值寄存器（804（1,1）804（1,4））和掩码值寄存器（806（1,1）至806（1,4））包括耦合下行中的CAM单元的输出的较低数据输入（LD）。

6. 发明授权

US5747868A Laser fusible link structure for semiconductor devices 失效
标题翻译：用于半导体器件的激光熔丝连接结构
公开(公告)号：US5747868A
公开(公告)日：1998-05-05
申请号：US494890
申请日：1995-06-26
申请人： Chitranjan N. Reddy , Ajit K. Medhekar
发明人： Chitranjan N. Reddy , Ajit K. Medhekar
IPC分类号： H01L23/525 , H01L29/00
CPC分类号： H01L23/5258 , H01L2924/0002
摘要： An improved laser fusible link structure for semiconductor devices (200) and method of manufacturing thereof (10) is disclosed. A first conductive layer is patterned to create a laser fuse (202) and then covered with a first dielectric layer (212). An etch mask layer, in the preferred embodiment a second layer of polysilicon, is deposited and patterned to form a fuse etch mask (214) directly over the laser fuse (202). The fuse etch mask (214) has a width that is smaller than a minimum laser spot size, but large enough to protect the laser fuse (202) from fuse window over-etch, taking into account any potential misalignment between the laser fuse (202) and the fuse etch mask (214).
摘要翻译：公开了一种用于半导体器件（200）的改进的激光熔丝连接结构及其制造方法（10）。图案化第一导电层以产生激光熔丝（202），然后用第一介电层（212）覆盖。在优选实施例中，蚀刻掩模层被沉积并图案化以在激光熔丝（202）的正上方形成熔丝蚀刻掩模（214）。保险丝蚀刻掩模（214）具有小于最小激光光斑尺寸的宽度，但足够大以保护激光熔丝（202）免受熔丝窗口过蚀刻，考虑到激光熔丝（202）之间的任何潜在的未对准）和熔丝蚀刻掩模（214）。

7. 发明授权

US5375097A Segmented bus architecture for improving speed in integrated circuit memories 失效
标题翻译：分段总线架构，用于提高集成电路存储器的速度
公开(公告)号：US5375097A
公开(公告)日：1994-12-20
申请号：US84010
申请日：1993-06-29
申请人： Chitranjan N. Reddy , Ajit K. Medhekar
发明人： Chitranjan N. Reddy , Ajit K. Medhekar
IPC分类号： G11C5/02 , G11C5/06 , G11C8/00
CPC分类号： G11C5/063 , G11C5/025
摘要： A memory array wherein transfer bus length is reduced and segmented by arranging the column decoder select signals to run across the length of the word line to reduce the node capacitance seen by the corresponding memory cell. This transfer of low capacitance from the transfer bus, i.e., the critical path, to the select line, which is a non-critical path for speed, improves access speed.
摘要翻译：一种存储器阵列，其中通过将列解码器选择信号布置成跨越字线的长度来减少和分段传输总线长度，以减小对应的存储器单元所看到的节点电容。将低电容从传输总线（即关键路径）传输到作为速度的非关键路径的选择线路提高了访问速度。

8. 发明授权

US5306958A High-speed address transition detection circuit 失效
标题翻译：高速地址转换检测电路
公开(公告)号：US5306958A
公开(公告)日：1994-04-26
申请号：US880968
申请日：1992-05-06
申请人： Chitranjan N. Reddy , Ajit K. Medhekar
发明人： Chitranjan N. Reddy , Ajit K. Medhekar
IPC分类号： G11C8/18 , H03K3/033 , H03K5/13 , H03K5/1534 , H03K3/017 , H03K5/22
CPC分类号： G11C8/18 , H03K3/033 , H03K5/13 , H03K5/1534
摘要： An address detection transition circuit provides an address transition detection pulse in response to either a high-to-low or a low-to-high external address input logic transition. The address transition detection circuit includes an address input buffer that responds to the external address input by providing first and second complimentary signals at first and second address input buffer output nodes, respectively. A first delay chain connected between the first address input buffer output node and the buffer output node responds to a high-to-low external address input logic transition by providing a logic high signal at the buffer output node. Similarly, a second delay chain connected between the second address input buffer output node and the buffer output node responds to a low-to-high external address input logic transition by providing a logic high signal at the buffer output node. A pull-down device responds to a logic high signal at the buffer output node by generating a logic low address transition detection pulse at the address transition detection node. A feedback controlled network connected to the address transition detection node controls the pulse width of the address transition detection pulse.
摘要翻译：地址检测转换电路响应于高到低或低到高的外部地址输入逻辑转换来提供地址转换检测脉冲。地址转换检测电路包括分别通过在第一和第二地址输入缓冲器输出节点处提供第一和第二互补信号来响应外部地址输入的地址输入缓冲器。连接在第一地址输入缓冲器输出节点和缓冲器输出节点之间的第一延迟链通过在缓冲器输出节点处提供逻辑高电平信号来响应高到低的外部地址输入逻辑转换。类似地，连接在第二地址输入缓冲器输出节点和缓冲器输出节点之间的第二延迟链通过在缓冲器输出节点处提供逻辑高电平信号来响应低到高的外部地址输入逻辑转换。下拉装置通过在地址转换检测节点处产生逻辑低地址转换检测脉冲来响应缓冲器输出节点处的逻辑高电平信号。连接到地址转换检测节点的反馈控制网络控制地址转换检测脉冲的脉冲宽度。

9. 发明授权

US06266262B1 Enhanced binary content addressable memory for longest prefix address matching 有权
标题翻译：增强的二进制内容可寻址内存，用于最长的前缀地址匹配
公开(公告)号：US06266262B1
公开(公告)日：2001-07-24
申请号：US09187285
申请日：1998-11-05
申请人： James G. Washburn , Jayan R. Ramankutty , Ajit K. Medhekar
发明人： James G. Washburn , Jayan R. Ramankutty , Ajit K. Medhekar
IPC分类号： G11C1504
CPC分类号： G11C15/04
摘要： A modified binary content addressable memory (CAM) (700) having a fast variable prefix matching capability is disclosed. The modified CAM (700) includes modified CAM cells (702(0,0) to 702(n,m)), each of which includes a store/compare circuit (704(0,0) to 704(n,m)) for storing a data value and comparing the data value to a comparand value. In addition, each modified CAM cell (702(0,0) to 702(n,m)) further includes a multiplexer (MUX) circuit (706(0,0) to 706(n,m)). Each MUX circuit (706(0,0) to 706(n,m)) receives a non-shifted comparand value from a modified CAM cell of a previous row and same column, and a shifted comparand value from a modified CAM cell of the previous row and an adjacent column. The MUX circuits (706(0,0) to 706(n,m)) enable a comparand value to be shifted as it is applied to consecutive data values.
摘要翻译：公开了具有快速可变前缀匹配能力的修改后的二进制内容可寻址存储器（CAM）（700）。修改的CAM（700）包括修改的CAM单元（702（0,0）至702（n，m）），每个单元包括存储/比较电路（704（0,0）至704（n，m）））用于存储数据值并将数据值与比较值进行比较。此外，每个修改的CAM单元（702（0,0）至702（n，m））还包括多路复用器（MUX）电路（706（0,0）至706（n，m）））。每个MUX电路（706（0,0）至706（n，m））从前一行和同一列的修改的CAM单元接收未移位的比较值，并且从修改的CAM单元上一行和相邻列。多路复用电路（706（0,0）至706（n，m））使比较值随着应用于连续的数据值而被移位。

10. 发明授权

US6025214A Fusible link structure for semiconductor devices 失效
标题翻译：用于半导体器件的可熔连接结构
公开(公告)号：US6025214A
公开(公告)日：2000-02-15
申请号：US956192
申请日：1997-10-22
申请人： Chitranjan N. Reddy , Ajit K. Medhekar
发明人： Chitranjan N. Reddy , Ajit K. Medhekar
IPC分类号： H01L23/525 , H01L21/82
CPC分类号： H01L23/5258 , H01L2924/0002
摘要： An improved laser fusible link structure for semiconductor devices (200) and method of manufacturing thereof (10) is disclosed. A first conductive layer is patterned to create a laser fuse (202) and then covered with a first dielectric layer (212). An etch mask layer, in the preferred embodiment a second layer of polysilicon, is deposited and patterned to form a fuse etch mask (214) directly over the laser fuse (202). The fuse etch mask (214) has a width that is smaller than a minimum laser spot size, but large enough to protect the laser fuse (202) from fuse window over-etch, taking into account any potential misalignment between the laser fuse (202) and the fuse etch mask (214).
摘要翻译：公开了一种用于半导体器件（200）的改进的激光熔丝连接结构及其制造方法（10）。图案化第一导电层以产生激光熔丝（202），然后用第一介电层（212）覆盖。在优选实施例中，蚀刻掩模层被沉积并图案化以在激光熔丝（202）的正上方形成熔丝蚀刻掩模（214）。保险丝蚀刻掩模（214）具有小于最小激光光斑尺寸的宽度，但足够大以保护激光熔丝（202）免受熔丝窗口过蚀刻，考虑到激光熔丝（202）之间的任何潜在的未对准）和熔丝蚀刻掩模（214）。

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