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1. 发明授权

US4851852A Decorrelation tolerant coherent radar altimeter 失效
标题翻译：相关容差相干雷达测高仪
公开(公告)号：US4851852A
公开(公告)日：1989-07-25
申请号：US40436
申请日：1987-04-20
申请人： Merlin D. Bjorke , Baard H. Thue
发明人： Merlin D. Bjorke , Baard H. Thue
IPC分类号： G01S7/28 , G01S13/10 , G01S13/32 , G01S13/88
CPC分类号： G01S13/32 , G01S13/10 , G01S7/28 , G01S13/882
摘要： A pulsed coherent radar altimeter is described which employs a narrow band receiver and utilizes a novel digital coherent pulse generator. A coherent pulse radar transmits a pulse comprised of the sum of at least two phase related RF signals closely spaced in frequency. The phase shift due to platform motion and return surface irregularity of the return signal is approximately the same for each carrier. The receiver produces a signal representative of the difference of the two carriers which is substantially free of decorrelation effects, and which can be processed in a narrow band receiver to produce range information.

2. 发明授权

US4959654A Digitally generated two carrier phase coded signal source 失效
标题翻译：数字生成两个载波相位编码信号源
公开(公告)号：US4959654A
公开(公告)日：1990-09-25
申请号：US241688
申请日：1988-09-07
申请人： Merlin D. Bjorke , Baard H. Thue
发明人： Merlin D. Bjorke , Baard H. Thue
IPC分类号： G01S7/28 , G01S13/10 , G01S13/32 , G01S13/88
CPC分类号： G01S7/28 , G01S13/10 , G01S13/32 , G01S13/882
摘要： A high frequency signal is converted to a signal characteristic of two simultaneously present, closely spaced high frequency signals. A high frequency signal is passed through a controllable bi-phase modulating switch. The switch is controlled by the resultant output of a multiplier which multiplies the sign of two phase-related pulse trains.
摘要翻译：高频信号被转换为两个同时存在的紧密间隔的高频信号的信号特征。高频信号通过可控双相调制开关。开关由乘法器的合成输出控制，乘法器乘以两个相位相关的脉冲序列的符号。

3. 再颁专利

USRE31145E Interruptable signal generator 失效
标题翻译：可中断信号发生器
公开(公告)号：USRE31145E
公开(公告)日：1983-02-08
申请号：US337217
申请日：1982-01-06
申请人： Merlin D. Bjorke
发明人： Merlin D. Bjorke
IPC分类号： H03K5/135
CPC分类号： H03K5/135
摘要： A circuit comprising a signal generating circuit and an interrupt enable circuit. The signal generating circuit has an input connected to receive a trigger signal and an output for generating an output signal which includes a timing cycle of known duration. The signal generating circuit is responsive to the trigger signal for initiating the timing cycle. The interrupt enable circuit is connected to the signal generating circuit for interrupting the timing cycle in timed relation to an interrupt signal and for reinitiating the timing cycle in timed relation to a reset signal, the interrupt enable circuit being connected to receive the interrupt and reset signals. The output signal begins in timed relation to the start pulse and terminates in timed relation to the end of the timing cycle following interruption.

4. 再颁专利

USRE31551E Digital delay generator 失效
标题翻译：数字延迟发生器
公开(公告)号：USRE31551E
公开(公告)日：1984-04-10
申请号：US336009
申请日：1981-12-30
申请人： Merlin D. Bjorke
发明人： Merlin D. Bjorke
IPC分类号： H03K5/135
CPC分类号： H03K5/135
摘要： Circuitry for generating a virtually jitter free delay relative to a start pulse and for generating such delays over both integer and non-integer multiples of the time interval between timing pulses. The circuitry includes delay circuitry and signal generating circuitry. The delay circuitry is responsive to the start pulse and to the timing pulses for generating first and second signal edges. The second signal edge occurs later in time than the first signal edge, and both signal edges occur following the start pulse and in timed relation to the timing pulses. The signal generating circuitry is connected to the delay circuitry and has an output for generating an output signal which includes a timing cycle of known duration. The signal generating circuitry is responsive to the start pulse for initiating the timing cycle, the first signal edge for interrupting the timing cycle, and the second signal edge for reinitiating the timing cycle. The output signal begins in timed relation to the start pulse and terminates in timed relation to the end of the timing cycle following interruption.

5. 发明授权

US4816834A Pulse synchronizing apparatus 失效
标题翻译：脉冲同步装置
公开(公告)号：US4816834A
公开(公告)日：1989-03-28
申请号：US188106
申请日：1988-04-27
申请人： Merlin D. Bjorke
发明人： Merlin D. Bjorke
IPC分类号： G01S13/32 , H04L7/04 , G01S13/08
CPC分类号： G01S13/325 , H04L7/043
摘要： Disclosed is a radar apparatus including the circuitry for synchronizing a first and second pulse train, having the same pseudo random coding. The apparatus comprises a programmable delay responsive to a control signal for selectively advancing and retarding a pulse train by monotonic increments. A positive and negative range gate is utilized in passing the video signals in opposite senses in order to generate a command signal for bringing the pulse trains in synchronization.
摘要翻译：公开了一种雷达装置，其包括用于同步具有相同伪随机编码的第一和第二脉冲串的电路。该装置包括响应于控制信号的可编程延迟，用于通过单调增量选择性地推进和延迟脉冲串。为了产生用于使脉冲串同步的命令信号，利用正和负范围门以相反的方式传递视频信号。

6. 发明授权

US4262222A Interruptable signal generator 失效
标题翻译：可中断信号发生器
公开(公告)号：US4262222A
公开(公告)日：1981-04-14
申请号：US968534
申请日：1978-12-11
申请人： Merlin D. Bjorke
发明人： Merlin D. Bjorke
IPC分类号： H03K5/135 , H03K17/28
CPC分类号： H03K5/135
摘要： A circuit comprising a signal generating circuit and an interrupt enable circuit. The signal generating circuit has an input connected to receive a trigger signal and an output for generating an output signal which includes a timing cycle of known duration. The signal generating circuit is responsive to the trigger signal for initiating the timing cycle. The interrupt enable circuit is connected to the signal generating circuit for interrupting the timing cycle in timed relation to an interrupt signal and for reinitiating the timing cycle in timed relation to a reset signal, the interrupt enable circuit being connected to receive the interrupt and reset signals. The output signal begins in timed relation to the start pulse and terminates in timed relation to the end of the timing cycle following interruption.
摘要翻译：一种包括信号发生电路和中断使能电路的电路。信号发生电路具有连接的输入端以接收触发信号和用于产生包括已知持续时间的定时周期的输出信号的输出。信号发生电路响应触发信号以启动定时周期。中断使能电路连接到信号发生电路，用于以与中断信号定时关系的定时周期中断，并以与复位信号定时关系重启定时周期，中断使能电路被连接以接收中断和复位信号。输出信号以起始脉冲的定时关系开始，并以与中断之后的定时周期结束的定时关系终止。

7. 发明授权

US4260912A Digital delay generator 失效
标题翻译：数字延迟发生器
公开(公告)号：US4260912A
公开(公告)日：1981-04-07
申请号：US968535
申请日：1978-12-11
申请人： Merlin D. Bjorke
发明人： Merlin D. Bjorke
IPC分类号： H03K5/135 , H03K17/28
CPC分类号： H03K5/135
摘要： Circuitry for generating a virtually jitter free delay relative to a start pulse and for generating such delays over both integer and non-integer multiples of the time interval between timing pulses. The circuitry includes delay circuitry and signal generating circuitry. The delay circuitry is responsive to the start pulse and to the timing pulses for generating first and second signal edges. The second signal edge occurs later in time than the first signal edge, and both signal edges occur following the start pulse and in timed relation to the timing pulses. The signal generating circuitry is connected to the delay circuitry and has an output for generating an output signal which includes a timing cycle of known duration. The signal generating circuitry is responsive to the start pulse for initiating the timing cycle, the first signal edge for interrupting the timing cycle, and the second signal edge for reinitiating the timing cycle. The output signal begins in timed relation to the start pulse and terminates in timed relation to the end of the timing cycle following interruption.
摘要翻译：用于产生相对于起始脉冲的实际无抖动延迟并用于在定时脉冲之间的时间间隔的整数倍和非整数倍之间产生这种延迟的电路。电路包括延迟电路和信号发生电路。延迟电路响应于起始脉冲和用于产生第一和第二信号边缘的定时脉冲。第二信号沿时间比第一信号边沿发生的时间晚，并且两个信号边沿都在起始脉冲之后发生，并且与定时脉冲成定时关系。信号发生电路连接到延迟电路，并且具有用于产生包括已知持续时间的定时周期的输出信号的输出。信号发生电路响应于起始脉冲以启动定时周期，用于中断定时周期的第一信号边缘和用于重新启动定时周期的第二信号边沿。输出信号以起始脉冲的定时关系开始，并以与中断之后的定时周期结束的定时关系终止。

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