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1. 发明授权

US06391771B1 Integrated circuit interconnect lines having sidewall layers 失效
标题翻译：具有侧壁层的集成电路互连线
公开(公告)号：US06391771B1
公开(公告)日：2002-05-21
申请号：US09121236
申请日：1998-07-23
申请人： Mehul B. Naik , Suketu A. Parikh
发明人： Mehul B. Naik , Suketu A. Parikh
IPC分类号： H01L2144
CPC分类号： H01L23/53233 , H01L21/28568 , H01L21/76834 , H01L21/76852 , H01L21/76885 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides Cu lines which are enclosed within Cu diffusion barrier layers, for IC structures such as semiconductor devices. The Cu lines (310) have conventional top (316) and bottom (318) Cu diffusion barrier layers and novel sidewall layers (324 and 326) comprising Cu diffusion barrier materials. The present invention also provides for conductive interconnect lines for semiconductor devices which compensate partly or completely for a misalignment between the line etch pattern and the underlying contact element, such as a via plug. The misalignment tolerant line (430) is formed by fabricating novel sidewalls (438 and 440) on the line wherein the sidewalls have a thickness which equals or exceeds the width of the gap (431) which is caused by the misalignment. The misalignment tolerant line compensates for the misalignment gap and thereby prevents etching a trench in the contact element. Trench formation is reduced rather than prevented when the sidewall is thinner than the width of the misalignment gap. In additional embodiments, manufacturing systems (510) are provided for fabricating the structures of the present invention. These systems include a controller (500) which is adapted for interacting with a plurality of fabrication stations (520, 522, 524, 526 and 528).
摘要翻译：本发明提供了用于诸如半导体器件的IC结构的包围在Cu扩散阻挡层内的Cu线。 Cu线（310）具有常规的顶部（316）和底部（318）Cu扩散阻挡层和包含Cu扩散阻挡材料的新颖侧壁层（324和326）。本发明还提供用于半导体器件的导电互连线，其部分地或完全地补偿线蚀刻图案和下面的接触元件（例如通孔插头）之间的未对准。通过在线路上制造新颖的侧壁（438和440）形成不对准容限线（430），其中侧壁具有等于或超过由未对准引起的间隙（431）的宽度的厚度。不对准容限线补偿了不对准间隙，从而防止蚀刻接触元件中的沟槽。当侧壁比不对准间隙的宽度更薄时，减小沟槽形成而不是防止沟槽形成。在另外的实施例中，提供制造系统（510）用于制造本发明的结构。这些系统包括适于与多个制造站（520,522,524,526和528）相互作用的控制器（500）。

2. 发明授权

US06514671B1 Interconnect line formed by dual damascene using dielectric layers having dissimilar etching characteristics 有权
标题翻译：使用具有不同蚀刻特性的电介质层由双镶嵌线形成的互连线
公开(公告)号：US06514671B1
公开(公告)日：2003-02-04
申请号：US09675989
申请日：2000-09-29
申请人： Suketu A. Parikh , Mehul B. Naik , Samuel Broydo , H. Peter W. Hey
发明人： Suketu A. Parikh , Mehul B. Naik , Samuel Broydo , H. Peter W. Hey
IPC分类号： G03C500
CPC分类号： H01L21/76808 , H01L23/485 , H01L2221/1031 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides integrated circuit fabrication methods and devices wherein dual damascene structures (332 and 334) are formed in consecutive dielectric layers (314 and 316) having dissimilar etching characteristics. The present invention also provides for such methods and devices wherein these dielectric layers have different dielectric constants. Additional embodiments of the present invention include the use of single layer masks, such as silicon-based photosensitive materials which form a hard mask (622) upon exposure to radiation. In additional embodiments, manufacturing systems (710) are provided for fabricating IC structures. These systems include a controller (700) which is adapted for interacting with a plurality of fabrication stations (720, 722, 724, 726, 728 and 730).
摘要翻译：本发明提供集成电路制造方法和装置，其中双镶嵌结构（332和334）形成在具有不同蚀刻特性的连续介电层（314和316）中。本发明还提供了这样的方法和装置，其中这些介电层具有不同的介电常数。本发明的另外的实施方案包括使用单层掩模，例如在暴露于辐射时形成硬掩模（622）的硅基感光材料。在另外的实施例中，制造系统（710）用于制造IC结构。这些系统包括适于与多个制造站（720,722,724,726,728和730）相互作用的控制器（700）。

3. 发明授权

US08951911B2 Process for damascene structure with reduced low-k damage 有权
标题翻译：具有降低低k损伤的镶嵌结构的工艺
公开(公告)号：US08951911B2
公开(公告)日：2015-02-10
申请号：US13174621
申请日：2011-06-30
申请人： Mehul B. Naik , Zhenjiang Cui
发明人： Mehul B. Naik , Zhenjiang Cui
IPC分类号： H01L21/44 , H01L21/02 , H01L21/768
CPC分类号： H01L21/02697 , H01L21/7681 , H01L21/76834 , H01L21/7685 , H01L21/76856 , H01L21/76873 , H01L21/76885 , H01L29/66583
摘要： Embodiments described herein generally provide methods for reducing undesired low-k damages during a damascene process using a sacrificial dielectric material and optionally a barrier/capping layer. In one embodiment, a damascene structure is formed through a sacrificial dielectric material deposited over a dielectric base layer. The damascene structure is filled with a suitable metal such as copper. The sacrificial dielectric material filled in trench areas between the copper damascene is then removed, followed by a barrier/cap layer which conformally or selectively covers exposed surfaces of the copper damascene structure. Ultra low-k dielectric materials may then fill the trench areas that were previously filled with sacrificial dielectric material. The invention prevents the ultra low-k material between the metal lines from exposing to various damaging processes during a damascene process such as etching, stripping, wet cleaning, pre-metal cleaning or CMP process.
摘要翻译：本文描述的实施例通常提供用于在使用牺牲介电材料和任选的阻挡/覆盖层的镶嵌工艺期间减少不希望的低k损伤的方法。在一个实施例中，通过沉积在电介质基底层上的牺牲绝缘材料形成镶嵌结构。镶嵌结构填充有合适的金属如铜。填充在铜镶嵌之间的沟槽区域中的牺牲介电材料然后被去除，随后是保形或选择性地覆盖铜镶嵌结构的暴露表面的阻挡层/盖层。然后，超低k电介质材料可以填充先前填充有牺牲介电材料的沟槽区域。本发明防止金属线之间的超低k材料在蚀刻，剥离，湿法清洗，金属前清洗或CMP工艺的大马士革处理过程中暴露于各种破坏性工艺。

4. 发明授权

US06514857B1 Damascene structure fabricated using a layer of silicon-based photoresist material 有权
公开(公告)号：US06514857B1
公开(公告)日：2003-02-04
申请号：US09788164
申请日：2001-02-16
申请人： Mehul B. Naik , Tim Weidman , Dian Sugiarto , Allen Zhao
发明人： Mehul B. Naik , Tim Weidman , Dian Sugiarto , Allen Zhao
IPC分类号： H01L214763
CPC分类号： H01L21/31144 , H01L21/0212 , H01L21/02271 , H01L21/02282 , H01L21/0332 , H01L21/3121 , H01L21/76802 , H01L21/76807 , H01L21/7681 , H01L21/76811 , H01L21/76813 , H01L21/76829 , H01L21/76835 , H01L2221/1021 , Y10S438/942
摘要： A damascene structure, and a method of fabricating same, containing relatively low dielectric constant materials (e.g., k less than 3.8). A silicon-based, photosensitive material, such as plasma polymerized methylsilane (PPMS), is used to form both single and dual damascene structures containing low k materials. During the manufacturing process that forms the damascene structures, the silicon-based photosensitive material is used as both a hard mask and/or an etch stop.

5. 发明授权

US07910476B2 Adhesion and minimizing oxidation on electroless CO alloy films for integration with low K inter-metal dielectric and etch stop 失效
标题翻译：粘附和最小化无电解CO合金膜上的氧化，用于与低K金属间电介质和蚀刻停止集成
公开(公告)号：US07910476B2
公开(公告)日：2011-03-22
申请号：US12240744
申请日：2008-09-29
申请人： Hongbin Fang , Timothy Weidman , Fang Mei , Yaxin Wang , Arulkumar Shanmugasundram , Christopher D. Bencher , Mehul B. Naik
发明人： Hongbin Fang , Timothy Weidman , Fang Mei , Yaxin Wang , Arulkumar Shanmugasundram , Christopher D. Bencher , Mehul B. Naik
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76829 , H01L21/76846 , H01L21/76849 , H01L21/76862 , H01L21/76864
摘要： A method and apparatus for processing a semiconductor substrate including depositing a capping layer upon a conductive material formed on the substrate, reducing oxide formation on the capping layer, and then depositing a dielectric material. A method and apparatus for processing a semiconductor substrate including depositing a capping layer upon a conductive material formed on a substrate, exposing the capping layer to a plasma, heating the substrate to more than about 100° C., and depositing a low dielectric constant material.
摘要翻译：一种用于处理半导体衬底的方法和装置，包括在形成在衬底上的导电材料上沉积覆盖层，减少覆盖层上的氧化物形成，然后沉积电介质材料。一种用于处理半导体衬底的方法和装置，包括在形成在衬底上的导电材料上沉积覆盖层，将覆盖层暴露于等离子体，将衬底加热到大于约100℃，以及沉积低介电常数材料。

6. 发明申请

US20090029544A1 ADHESION AND MINIMIZING OXIDATION ON ELECTROLESS CO ALLOY FILMS FOR INTEGRATION WITH LOW K INTER-METAL DIELECTRIC AND ETCH STOP 失效
标题翻译：用于与低K金属介电和蚀刻停止集成的电解CO合金膜上的粘合和最小化氧化
公开(公告)号：US20090029544A1
公开(公告)日：2009-01-29
申请号：US12240744
申请日：2008-09-29
申请人： Hongbin Fang , Timothy Weidman , Fang Mei , Yaxin Wang , Arulkumar Shanmugasundram , Christopher D. Bencher , Mehul B. Naik
发明人： Hongbin Fang , Timothy Weidman , Fang Mei , Yaxin Wang , Arulkumar Shanmugasundram , Christopher D. Bencher , Mehul B. Naik
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76829 , H01L21/76846 , H01L21/76849 , H01L21/76862 , H01L21/76864
摘要： A method and apparatus for processing a semiconductor substrate including depositing a capping layer upon a conductive material formed on the substrate, reducing oxide formation on the capping layer, and then depositing a dielectric material. A method and apparatus for processing a semiconductor substrate including depositing a capping layer upon a conductive material formed on a substrate, exposing the capping layer to a plasma, heating the substrate to more than about 100° C., and depositing a low dielectric constant material.
摘要翻译：一种用于处理半导体衬底的方法和装置，包括在形成在衬底上的导电材料上沉积覆盖层，减少覆盖层上的氧化物形成，然后沉积电介质材料。一种用于处理半导体衬底的方法和装置，包括在形成在衬底上的导电材料上沉积覆盖层，将覆盖层暴露于等离子体，将衬底加热到大于约100℃，以及沉积低介电常数材料。

7. 发明授权

US06169030A Metallization process and method 失效
标题翻译：金属化过程和方法
公开(公告)号：US06169030A
公开(公告)日：2001-01-02
申请号：US09007233
申请日：1998-01-14
申请人： Mehul B. Naik , Ted Guo , Liang-Yuh Chen , Roderick Craig Mosely , Israel Beinglass
发明人： Mehul B. Naik , Ted Guo , Liang-Yuh Chen , Roderick Craig Mosely , Israel Beinglass
IPC分类号： H01L2144
CPC分类号： C23C14/32 , C23C14/025 , C23C14/046 , H01L21/2855 , H01L21/76877
摘要： The invention generally provides an improved process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free interconnections in high aspect ratio, sub-half micron applications. The invention provides a multi-step PVD process in which the plasma power is varied for each of the steps to obtain favorable fill characteristics as well as good reflectivity, morphology and throughput. The initial plasma powers are relatively low to ensure good, void-free filling of the aperture and, then, the plasma powers are increased to obtain the desired reflectivity and morphology characteristics. The invention provides an aperture filling process comprising physical vapor depositing a metal over the substrate and varying the plasma power during the physical vapor deposition. Preferably, the plasma power is varied from a first discrete low plasma power to a second discrete high plasma power. Even more preferably, the plasma power is varied from a first discrete low plasma power to a second discrete low plasma power to a third discrete high plasma power.
摘要翻译：本发明通常提供了一种改进的方法，用于在衬底上提供均匀的台阶覆盖和金属层的平坦化，以在高纵横比，半微米应用中形成连续的无空隙互连。本发明提供了一种多步骤PVD工艺，其中等离子体功率对于每个步骤而言是变化的，以获得良好的填充特性以及良好的反射率，形态和产量。初始等离子体功率相对较低，以确保孔的良好的无空隙填充，然后增加等离子体功率以获得期望的反射率和形态特征。本发明提供一种孔填充方法，其包括在物理气相沉积中物理气相沉积衬底上的金属并改变等离子体功率。优选地，等离子体功率从第一离散低等离子体功率变化到第二离散高等离子体功率。更优选地，等离子体功率从第一离散低等离子体功率变化到第二离散低等离子体功率到第三离散高等离子体功率。

8. 发明申请

US20090286402A1 METHOD FOR CRITICAL DIMENSION SHRINK USING CONFORMAL PECVD FILMS 审中-公开
标题翻译：使用一致的PECVD膜的关键尺寸收缩的方法
公开(公告)号：US20090286402A1
公开(公告)日：2009-11-19
申请号：US12257137
申请日：2008-10-23
申请人： Li-Qun Xia , Mihaela Balseanu , Meiyee Shek , Siyi Li , Zhenjiang Cui , Mehul B. Naik , Michael D. Armacost , William H. McClintock
发明人： Li-Qun Xia , Mihaela Balseanu , Meiyee Shek , Siyi Li , Zhenjiang Cui , Mehul B. Naik , Michael D. Armacost , William H. McClintock
IPC分类号： H01L21/311
CPC分类号： H01L21/31144 , H01L21/02112 , H01L21/0217 , H01L21/02274 , H01L21/0337 , H01L21/0338 , H01L21/3141 , H01L21/31608 , H01L21/318 , H01L21/3185 , H01L21/76816
摘要： A method and apparatus for forming narrow vias in a substrate is provided. A pattern recess is etched into a substrate by conventional lithography. A thin conformal layer is formed over the surface of the substrate, including the sidewalls and bottom of the pattern recess. The thickness of the conformal layer reduces the effective width of the pattern recess. The conformal layer is removed from the bottom of the pattern recess by anisotropic etching to expose the substrate beneath. The substrate is then etched using the conformal layer covering the sidewalls of the pattern recess as a mask. The conformal layer is then removed using a wet etchant.
摘要翻译：提供了一种用于在基板中形成窄通孔的方法和装置。通过常规光刻将图案凹槽蚀刻到基底中。在衬底的表面上形成薄的共形层，包括图案凹槽的侧壁和底部。共形层的厚度减小了图案凹槽的有效宽度。通过各向异性蚀刻从图案凹槽的底部去除共形层以暴露下面的衬底。然后使用覆盖图案凹槽的侧壁的保形层作为掩模蚀刻衬底。然后使用湿蚀刻剂除去保形层。

9. 发明授权

US07226853B2 Method of forming a dual damascene structure utilizing a three layer hard mask structure 失效
标题翻译：使用三层硬掩模结构形成双镶嵌结构的方法
公开(公告)号：US07226853B2
公开(公告)日：2007-06-05
申请号：US10197936
申请日：2002-07-16
申请人： Nikolaos Bekiaris , Timothy Weidman , Michael D. Armacost , Mehul B. Naik
发明人： Nikolaos Bekiaris , Timothy Weidman , Michael D. Armacost , Mehul B. Naik
IPC分类号： H01L21/4763
CPC分类号： H01L21/022 , H01L21/02115 , H01L21/02126 , H01L21/02203 , H01L21/0332 , H01L21/31144 , H01L21/312 , H01L21/3146 , H01L21/76811 , H01L21/76813 , H01L21/76829 , H01L21/76835
摘要： A method of forming a dual damascene structure on a substrate having a dielectric layer already formed thereon. In one embodiment the method includes depositing a first hard mask layer over the dielectric layer; depositing a second hard mask layer on the first hard mask layer; depositing a third hard mask layer on the second hard mask layer and completing formation of the dual damascene structure by etching a metal wiring pattern and a via pattern in the dielectric layer and filling the etched metal wiring pattern and via pattern with a conductive material. In one particular embodiment the second hard mask layer is an amorphous carbon layer and the third hard mask layer is a silicon-containing material.
摘要翻译：在其上已经形成有电介质层的基板上形成双镶嵌结构的方法。在一个实施例中，该方法包括在介电层上沉积第一硬掩模层; 在第一硬掩模层上沉积第二硬掩模层; 在第二硬掩模层上沉积第三硬掩模层，并通过蚀刻电介质层中的金属布线图案和通孔图案并用导电材料填充蚀刻的金属布线图案和通孔图案，完成双镶嵌结构的形成。在一个特定实施例中，第二硬掩模层是无定形碳层，第三硬掩模层是含硅材料。

10. 发明授权

US06825562B2 Damascene structure fabricated using a layer of silicon-based photoresist material 失效
标题翻译：使用硅基光致抗蚀剂材料层制造的镶嵌结构
公开(公告)号：US06825562B2
公开(公告)日：2004-11-30
申请号：US10290637
申请日：2002-11-08
申请人： Mehul B. Naik , Tim Weidman , Dian Sugiarto , Allen Zhao
发明人： Mehul B. Naik , Tim Weidman , Dian Sugiarto , Allen Zhao
IPC分类号： H01L2348
CPC分类号： H01L21/31144 , H01L21/0212 , H01L21/02271 , H01L21/02282 , H01L21/0332 , H01L21/3121 , H01L21/76802 , H01L21/76807 , H01L21/7681 , H01L21/76811 , H01L21/76813 , H01L21/76829 , H01L21/76835 , H01L2221/1021 , Y10S438/942
摘要： A damascene structure, and a method of fabricating same, containing relatively low dielectric constant materials (e.g., k less than 3.8). A silicon-based, photosensitive material, such as plasma polymerized methylsilane (PPMS), is used to form both single and dual damascene structures containing low k materials. During the manufacturing process that forms the damascene structures, the silicon-based photosensitive material is used as both a hard mask and/or an etch stop.
摘要翻译：一种镶嵌结构及其制造方法，其包含相当低的介电常数材料（例如，k小于3.8）。使用诸如等离子体聚合甲基硅烷（PPMS）的硅基感光材料来形成含有低k材料的单镶嵌和双镶嵌结构。在形成镶嵌结构的制造过程中，将硅基感光材料用作硬掩模和/或蚀刻停止物。

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