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1. 发明授权

US09298618B1 Managing cache memory in a parallel processing environment 有权
标题翻译：在并行处理环境中管理高速缓存
公开(公告)号：US09298618B1
公开(公告)日：2016-03-29
申请号：US14154277
申请日：2014-01-14
申请人： Matthew Mattina
发明人： David Wentzlaff , Matthew Mattina , Anant Agarwal
IPC分类号： G06F15/163 , G06F12/08 , G06F12/10
CPC分类号： G06F13/24 , G06F12/0808 , G06F12/0813 , G06F12/0815 , G06F12/1027 , G06F12/1045 , G06F13/16 , G06F13/4022 , G06F2212/60 , G06F2212/621 , G06F2212/682 , H04L49/109
摘要： An apparatus comprises a plurality of processor cores, each comprising a computation unit and a memory. The apparatus further comprises an interconnection network to transmit data among the processor cores. At least some of the memories are configured as a cache for memory external to the processor cores, and at least some of the processor cores are configured to transmit a message over the interconnection network to access a cache of another processor core.
摘要翻译：一种装置包括多个处理器核心，每个处理器核心包括计算单元和存储器。该装置还包括互连网络以在处理器核心之间传送数据。至少一些存储器被配置为处理器核心外部的存储器的高速缓存，并且至少一些处理器核心被配置为通过互连网络传送消息以访问另一处理器核心的高速缓存。

2. 发明授权

US07620791B1 Mapping memory in a parallel processing environment 有权
标题翻译：在并行处理环境中映射内存
公开(公告)号：US07620791B1
公开(公告)日：2009-11-17
申请号：US11404207
申请日：2006-04-14
申请人： David Wentzlaff , Matthew Mattina , Anant Agarwal
发明人： David Wentzlaff , Matthew Mattina , Anant Agarwal
IPC分类号： G06F12/08
CPC分类号： G06F12/1027 , G06F12/0815 , G06F12/084 , G06F12/0844
摘要： An integrated circuit comprises a plurality of tiles. Each tile comprises a processor, and a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles. The integrated circuit further includes a plurality of memory interface modules including circuitry to access a respective external memory, each memory interface module coupled to a switch of at least one tile. At least some of the tiles are configured to access an address in an external memory by sending from the switch a packet that includes a physical memory address that includes the external memory address and information identifying the corresponding external memory.
摘要翻译：集成电路包括多个瓦片。每个瓦片包括处理器和开关，其包括切换电路，用于将通过数据路径从其他瓦片接收的数据转发到处理器，并转换到其他瓦片，以及将从处理器接收的数据转发到其他瓦片的切换。集成电路还包括多个存储器接口模块，其包括用于访问相应的外部存储器的电路，每个存储器接口模块耦合到至少一个瓦片的开关。至少一些瓦片被配置为通过从交换机发送包括包括外部存储器地址的物理存储器地址和识别对应的外部存储器的信息的分组来访问外部存储器中的地址。

3. 发明授权

US07461210B1 Managing set associative cache memory according to entry type 有权
标题翻译：根据条目类型管理集合关联高速缓存
公开(公告)号：US07461210B1
公开(公告)日：2008-12-02
申请号：US11404654
申请日：2006-04-14
申请人： David Wentzlaff , Matthew Mattina , Anant Agarwal
发明人： David Wentzlaff , Matthew Mattina , Anant Agarwal
IPC分类号： G06F12/06
CPC分类号： G06F12/126 , G06F12/0864 , G06F2212/1021
摘要： Managing memory includes: mediating access to a first memory as a cache for a second memory; and associating one of a plurality of entry types with entries in the cache. Data from the second memory associated with a first type is not allowed to evict a cache entry associated with a second type.
摘要翻译：管理存储器包括：将作为第二存储器的缓存的第一存储器的访问中介; 以及将多个条目类型中的一个与所述高速缓存中的条目相关联。来自与第一类型相关联的第二存储器的数据不允许驱逐与第二类型相关联的高速缓存条目。

4. 发明授权

US07805577B1 Managing memory access in a parallel processing environment 有权
标题翻译：在并行处理环境中管理内存访问
公开(公告)号：US07805577B1
公开(公告)日：2010-09-28
申请号：US11404655
申请日：2006-04-14
申请人： Matthew Mattina , David Wentzlaff , Anant Agarwal
发明人： Matthew Mattina , David Wentzlaff , Anant Agarwal
IPC分类号： G06F12/06
CPC分类号： G06F12/0817 , G06F12/0842 , G06F12/0875 , G06F12/1036 , Y02D10/13
摘要： An integrated circuit comprises a plurality of tiles. Each tile comprises a processor, and a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles. The integrated circuit further comprises one or more memory interface modules including circuitry to access an external memory, each memory interface module coupled to a switch of at least one tile. At least some of the tiles are configured to send a message to a memory interface module to determine whether previous memory transactions associated with a tile have been completed.
摘要翻译：集成电路包括多个瓦片。每个瓦片包括处理器和开关，其包括切换电路，用于将通过数据路径从其他瓦片接收的数据转发到处理器，并转换到其他瓦片，以及将从处理器接收的数据转发到其他瓦片的切换。集成电路还包括一个或多个存储器接口模块，其包括用于访问外部存储器的电路，每个存储器接口模块耦合到至少一个瓦片的开关。至少一些瓦片被配置为向存储器接口模块发送消息以确定与瓦片相关联的先前存储器事务是否已经完成。

5. 发明授权

US08200901B1 Managing cache memory in a parallel processing environment 有权
标题翻译：在并行处理环境中管理高速缓存
公开(公告)号：US08200901B1
公开(公告)日：2012-06-12
申请号：US12983368
申请日：2011-01-03
申请人： David Wentzlaff , Matthew Mattina , Anant Agarwal
发明人： David Wentzlaff , Matthew Mattina , Anant Agarwal
IPC分类号： G06F12/08
CPC分类号： G06F13/24 , G06F12/0808 , G06F12/0813 , G06F12/0815 , G06F12/1027 , G06F12/1045 , G06F13/16 , G06F13/4022 , G06F2212/60 , G06F2212/621 , G06F2212/682 , H04L49/109
摘要： An apparatus comprises a plurality of processor cores, each comprising a computation unit and a memory. The apparatus further comprises an interconnection network to transmit data among the processor cores. At least some of the memories are configured as a cache for memory external to the processor cores, and at least some of the processor cores are configured to transmit a message over the interconnection network to access a cache of another processor core.
摘要翻译：一种装置包括多个处理器核心，每个处理器核心包括计算单元和存储器。该装置还包括互连网络以在处理器核心之间传送数据。至少一些存储器被配置为处理器核心外部的存储器的高速缓存，并且至少一些处理器核心被配置为通过互连网络传送消息以访问另一处理器核心的高速缓存。

6. 发明授权

US07882307B1 Managing cache memory in a parallel processing environment 有权
标题翻译：在并行处理环境中管理高速缓存
公开(公告)号：US07882307B1
公开(公告)日：2011-02-01
申请号：US11404641
申请日：2006-04-14
申请人： David Wentzlaff , Matthew Mattina , Anant Agarwal
发明人： David Wentzlaff , Matthew Mattina , Anant Agarwal
IPC分类号： G06F12/08
CPC分类号： G06F13/24 , G06F12/0808 , G06F12/0813 , G06F12/0815 , G06F12/1027 , G06F12/1045 , G06F13/16 , G06F13/4022 , G06F2212/60 , G06F2212/621 , G06F2212/682 , H04L49/109
摘要： An apparatus comprises a plurality of processor cores, each comprising a computation unit and a memory. The apparatus further comprises an interconnection network to transmit data among the processor cores. At least some of the memories are configured as a cache for memory external to the processor cores, and at least some of the processor cores are configured to transmit a message over the interconnection network to access a cache of another processor core.
摘要翻译：一种装置包括多个处理器核心，每个处理器核心包括计算单元和存储器。该装置还包括互连网络以在处理器核心之间传送数据。至少一些存储器被配置为处理器核心外部的存储器的高速缓存，并且至少一些处理器核心被配置为通过互连网络传送消息以访问另一处理器核心的高速缓存。

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