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1. 发明申请

US20070197037A1 Surface preparation for gate oxide formation that avoids chemical oxide formation 有权
标题翻译：防止化学氧化物形成的栅极氧化物形成的表面处理
公开(公告)号：US20070197037A1
公开(公告)日：2007-08-23
申请号：US11358624
申请日：2006-02-21
申请人： Matt Yeh , Shun Lin , Chi-Chun Chen , Shih-Chang Chen
发明人： Matt Yeh , Shun Lin , Chi-Chun Chen , Shih-Chang Chen
IPC分类号： B08B6/00 , H01L21/302 , H01L21/31
CPC分类号： H01L21/31111 , H01L21/0206 , H01L21/28167 , H01L21/31133 , H01L21/823462
摘要： A cleaning sequence usable in semiconductor manufacturing efficiently cleans semiconductor substrates while preventing chemical oxide formation thereon. The sequence includes the sequence of: 1) treating with an HF solution; 2) treating with pure H2SO4; 3) treating with an H2O2 solution; 4) a DI water rinse; and 5) treatment with an HCl solution. The pure H2SO4 solution may include an H2SO4 concentration of about ninety-eight percent (98%) or greater. After the HCl solution treatment, the cleaned surface may be a silicon surface that is free of a chemical oxide having a thickness of 5 angstroms or greater. The invention finds particular advantage in semiconductor devices that utilize multiple gate oxide thicknesses.
摘要翻译：可用于半导体制造的清洁顺序有效地清洁半导体衬底，同时防止其上形成化学氧化物。该序列包括以下顺序：1）用HF溶液处理; 2）用纯H 2 SO 4处理; 3）用H 2 O 2 O 2溶液处理; 4）去离子水冲洗; 和5）用HCl溶液处理。纯H 2 SO 4溶液可包括约百分之九十八的H 2 SO 4 SO 4浓度（ 98％）或更高。在HCl溶液处理之后，清洁的表面可以是不含厚度为5埃或更大的化学氧化物的硅表面。本发明在利用多个栅极氧化物厚度的半导体器件中具有特别的优点。

2. 发明申请

US20080096394A1 GATE DIELECTRIC LAYERS AND METHODS OF FABRICATING GATE DIELECTRIC LAYERS 有权
标题翻译：门电介质层和制造栅介质层的方法
公开(公告)号：US20080096394A1
公开(公告)日：2008-04-24
申请号：US11551577
申请日：2006-10-20
申请人： Chi-Chun Chen , Matt Yeh , Shih-Chang Chen , Mong-Song Liang , Jennifer Chen , Da-Yuan Lee
发明人： Chi-Chun Chen , Matt Yeh , Shih-Chang Chen , Mong-Song Liang , Jennifer Chen , Da-Yuan Lee
IPC分类号： H01L21/31
CPC分类号： H01L21/31155 , H01L21/02126 , H01L21/02211 , H01L21/02238 , H01L21/02255 , H01L21/02271 , H01L21/02321 , H01L21/0234 , H01L21/02351 , H01L21/26506 , H01L21/28185 , H01L21/2822 , H01L21/3141 , H01L21/31633 , H01L21/31662 , H01L21/823462
摘要： A method of forming a gate dielectric layer includes forming a gate dielectric layer over a substrate. The gate dielectric layer is processed with carbon-containing ions. The gate dielectric layer is thermally processed, thereby providing the gate dielectric layer with a level of carbon between about 1 atomic % and about 20 atomic %.
摘要翻译：形成栅极电介质层的方法包括在衬底上形成栅极电介质层。用含碳离子处理栅介质层。栅极电介质层被热处理，从而为栅极电介质层提供约1原子％至约20原子％之间的碳含量。

3. 发明申请

US20080060682A1 HIGH TEMPERATURE SPM TREATMENT FOR PHOTORESIST STRIPPING 审中-公开
标题翻译：用于光电子剥离的高温SPM处理
公开(公告)号：US20080060682A1
公开(公告)日：2008-03-13
申请号：US11531598
申请日：2006-09-13
申请人： Matt Yeh , Shun-Wu Lin , Chi-Chun Chen , Shih-Chang Chen
发明人： Matt Yeh , Shun-Wu Lin , Chi-Chun Chen , Shih-Chang Chen
IPC分类号： B08B3/00
CPC分类号： H01L21/31133 , G03F7/423
摘要： A method for stripping photoresist and cleaning a semiconductor substrate include a high temperature stripping process in a freshly mixed SPM solution followed by cleaning in a water soluble organic co-solvent such as acetone, IPA, methanol, ethanol, butanol, or DMSO. The substrate may undergo back side heating during the SPM solution stripping process and may optionally use nanospraying techniques to direct the water soluble organic co-solvent to the substrate. The method completely strips plasma hardened photoresist using only wet chemical operations.
摘要翻译：用于剥离光致抗蚀剂和清洁半导体衬底的方法包括在新混合的SPM溶液中的高温汽提过程，然后在水溶性有机共溶剂如丙酮，IPA，甲醇，乙醇，丁醇或DMSO中进行清洗。衬底可以在SPM溶液剥离过程期间进行背面加热，并且可以任选地使用纳米喷涂技术将水溶性有机共溶剂引导至基底。该方法仅使用湿化学操作完全剥离等离子体硬化的光致抗蚀剂。

4. 发明申请

US20060275975A1 Nitridated gate dielectric layer 审中-公开
标题翻译：氮化栅介质层
公开(公告)号：US20060275975A1
公开(公告)日：2006-12-07
申请号：US11142488
申请日：2005-06-01
申请人： Matt Yeh , Da-Yuan Lee , Chi-Chun Chen , Jin Ying , Shih-Chang Chen
发明人： Matt Yeh , Da-Yuan Lee , Chi-Chun Chen , Jin Ying , Shih-Chang Chen
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823842 , H01L29/785
摘要： A metal-oxide-semiconductor field-effect transistors (MOSFET) with a gate structure having a deuterated layer is provided. In accordance with embodiments of the present invention, a transistor comprises the deuterated layer formed over a gate dielectric layer. A gate electrode is formed over the deuterated layer. The deuterated layer prevents or reduces dopant penetration into a substrate from the gate electrode. The deuterated layer may be, for example, formed by a thermal process in an ambient of a deuterated gas, such as deuterated ammonia. The deuterated layer may also be formed by a nitridation process using deuterated ammonia.
摘要翻译：提供具有氘代层的栅极结构的金属氧化物半导体场效应晶体管（MOSFET）。根据本发明的实施例，晶体管包括在栅介电层上形成的氘化层。在氘化层上形成栅电极。氘化层防止或减少掺杂剂从栅电极渗透到衬底中。氘化层可以例如通过氘化气体的环境中的热过程形成，例如氘代氨。氘化层也可以通过使用氘代氨的氮化方法形成。

5. 发明授权

US07727900B2 Surface preparation for gate oxide formation that avoids chemical oxide formation 有权
标题翻译：防止化学氧化物形成的栅极氧化物形成的表面处理
公开(公告)号：US07727900B2
公开(公告)日：2010-06-01
申请号：US11358624
申请日：2006-02-21
申请人： Matt Yeh , Shun Wu Lin , Chi-Chun Chen , Shih-Chang Chen
发明人： Matt Yeh , Shun Wu Lin , Chi-Chun Chen , Shih-Chang Chen
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/31111 , H01L21/0206 , H01L21/28167 , H01L21/31133 , H01L21/823462
摘要： A cleaning sequence usable in semiconductor manufacturing efficiently cleans semiconductor substrates while preventing chemical oxide formation thereon. The sequence includes the sequence of: 1) treating with an HF solution; 2) treating with pure H2SO4; 3) treating with an H2O2 solution; 4) a DI water rinse; and 5) treatment with an HCl solution. The pure H2SO4 solution may include an H2SO4 concentration of about ninety-eight percent (98%) or greater. After the HCl solution treatment, the cleaned surface may be a silicon surface that is free of a chemical oxide having a thickness of 5 angstroms or greater. The invention finds particular advantage in semiconductor devices that utilize multiple gate oxide thicknesses.
摘要翻译：可用于半导体制造的清洁顺序有效地清洁半导体衬底，同时防止其上形成化学氧化物。该序列包括以下顺序：1）用HF溶液处理; 2）用纯H 2 SO 4处理; 3）用H 2 O 2溶液处理; 4）去离子水冲洗; 和5）用HCl溶液处理。纯H 2 SO 4溶液可以包括约百分之九十八（98％）或更高的H 2 SO 4浓度。在HCl溶液处理之后，清洁的表面可以是不含厚度为5埃或更大的化学氧化物的硅表面。本发明在利用多个栅极氧化物厚度的半导体器件中具有特别的优点。

6. 发明授权

US07713854B2 Gate dielectric layers and methods of fabricating gate dielectric layers 有权
标题翻译：栅极电介质层和制造栅极电介质层的方法
公开(公告)号：US07713854B2
公开(公告)日：2010-05-11
申请号：US11551577
申请日：2006-10-20
申请人： Chi-Chun Chen , Matt Yeh , Shih-Chang Chen , Mong-Song Liang , Jennifer Chen , Da-Yuan Lee
发明人： Chi-Chun Chen , Matt Yeh , Shih-Chang Chen , Mong-Song Liang , Jennifer Chen , Da-Yuan Lee
IPC分类号： H01L21/3205
CPC分类号： H01L21/31155 , H01L21/02126 , H01L21/02211 , H01L21/02238 , H01L21/02255 , H01L21/02271 , H01L21/02321 , H01L21/0234 , H01L21/02351 , H01L21/26506 , H01L21/28185 , H01L21/2822 , H01L21/3141 , H01L21/31633 , H01L21/31662 , H01L21/823462
摘要： A method of forming a gate dielectric layer includes forming a gate dielectric layer over a substrate. The gate dielectric layer is processed with carbon-containing ions. The gate dielectric layer is thermally processed, thereby providing the gate dielectric layer with a level of carbon between about 1 atomic % and about 20 atomic %.
摘要翻译：形成栅极电介质层的方法包括在衬底上形成栅极电介质层。用含碳离子处理栅介质层。栅极电介质层被热处理，从而为栅极电介质层提供约1原子％至约20原子％之间的碳含量。

7. 发明申请

US20080124861A1 Electron mobility enhancement for MOS devices with nitrided polysilicon re-oxidation 有权
标题翻译：具有氮化多晶硅再氧化的MOS器件的电子迁移率增强
公开(公告)号：US20080124861A1
公开(公告)日：2008-05-29
申请号：US11593293
申请日：2006-11-06
申请人： Wenli Lin , Da-Yuan Lee , Chi-Chun Chen , Shih-Chang Chen
发明人： Wenli Lin , Da-Yuan Lee , Chi-Chun Chen , Shih-Chang Chen
IPC分类号： H01L21/8238
CPC分类号： H01L21/823864 , H01L21/28247 , H01L29/66545 , H01L29/6656
摘要： A semiconductor structure includes a PMOS device and an NMOS device. The PMOS device includes a first gate dielectric on a semiconductor substrate, a first gate electrode on the first gate dielectric, and a first gate spacer along sidewalls of the first gate electrode and the first gate dielectric. The NMOS device includes a second gate dielectric on the semiconductor substrate, a second gate electrode on the second gate dielectric, a nitrided polysilicon re-oxidation layer having a vertical portion and a horizontal portion wherein the vertical portion is on sidewalls of the second gate electrode and the second gate dielectric and wherein the horizontal portion is on the semiconductor substrate, and a second gate spacer on sidewalls of the second gate electrode and the second gate dielectric, wherein the second gate spacer is on the horizontal portion of the nitrided polysilicon re-oxidation layer.
摘要翻译：半导体结构包括PMOS器件和NMOS器件。 PMOS器件包括半导体衬底上的第一栅极电介质，第一栅极电介质上的第一栅极电极和沿着第一栅极电极和第一栅极电介质的侧壁的第一栅极间隔物。所述NMOS器件包括在所述半导体衬底上的第二栅极电介质，所述第二栅极电介质上的第二栅极电极，具有垂直部分和水平部分的氮化多晶硅再氧化层，其中所述垂直部分位于所述第二栅电极的侧壁上和所述第二栅极电介质，并且其中所述水平部分在所述半导体衬底上，以及在所述第二栅极电极和所述第二栅极电介质的侧壁上的第二栅极间隔物，其中所述第二栅极间隔物位于所述氮化多晶硅的水平部分上，氧化层。

8. 发明申请

US20070166904A1 Pre-gate dielectric process using hydrogen annealing 有权
标题翻译：使用氢退火的预栅电介质工艺
公开(公告)号：US20070166904A1
公开(公告)日：2007-07-19
申请号：US11333399
申请日：2006-01-17
申请人： Jocelyn Teo , Chi-Chun Chen , Shih-Chang Chen
发明人： Jocelyn Teo , Chi-Chun Chen , Shih-Chang Chen
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/823828 , H01L21/823857
摘要： The preferred embodiment of the present invention provides a novel method of forming MOS devices using hydrogen annealing. The method includes providing a semiconductor substrate including a first region and a second region, forming at least a portion of a first MOS device covering at least a portion of the first active region, performing a hydrogen annealing in an ambient containing substantially pure hydrogen on the semiconductor substrate. The hydrogen annealing is performed after the step of the at least a portion of the first MOS device is formed, and preferably after a pre-oxidation cleaning. The method further includes forming a second MOS device in the second active region after hydrogen annealing. The hydrogen annealing causes the surface of the second active region to be substantially rounded, while the surface of the first active region is substantially flat.
摘要翻译：本发明的优选实施方案提供了使用氢退火形成MOS器件的新方法。该方法包括提供包括第一区域和第二区域的半导体衬底，形成覆盖第一有源区域的至少一部分的第一MOS器件的至少一部分，在包含基本上纯氢的环境中进行氢退火半导体衬底。氢退火在形成第一MOS器件的至少一部分的步骤之后，优选在预氧化清洗之后进行。该方法还包括在氢退火之后在第二有源区中形成第二MOS器件。氢退火使得第二有源区的表面基本上是圆形的，而第一有源区的表面基本上是平的。

9. 发明授权

US07166525B2 High temperature hydrogen annealing of a gate insulator layer to increase etching selectivity between conductive gate structure and gate insulator layer 有权
标题翻译：栅极绝缘体层的高温氢退火以增加导电栅极结构和栅极绝缘体层之间的蚀刻选择性
公开(公告)号：US07166525B2
公开(公告)日：2007-01-23
申请号：US10758317
申请日：2004-01-15
申请人： Vincent S. Chang , Chia-Lin Chen , Chi-Chun Chen , Tze-Liang Lee , Shih-Chang Chen , Chien-Hao Chen
发明人： Vincent S. Chang , Chia-Lin Chen , Chi-Chun Chen , Tze-Liang Lee , Shih-Chang Chen , Chien-Hao Chen
IPC分类号： H01L21/4763 , H01L21/3205
CPC分类号： H01L29/518 , H01L21/28123 , H01L21/28185 , H01L21/28202 , H01L21/3105 , H01L21/3144 , H01L21/32137 , H01L29/6659
摘要： A method of defining a conductive gate structure for a MOSFET device wherein the etch rate selectivity of the conductive gate material to an underlying insulator layer is optimized, has been developed. After formation of a nitrided silicon dioxide layer, to be used as for the MOSFET gate insulator layer, a high temperature hydrogen anneal procedure is performed. The high temperature anneal procedure replaces nitrogen components in a top portion of the nitrided silicon dioxide gate insulator layer with hydrogen components. The etch rate of the hydrogen annealed layer in specific dry etch ambients is now decreased when compared to the non-hydrogen annealed nitrided silicon dioxide counterpart. Thus the etch rate selectivity of conductive gate material to underlying gate insulator material is increased when employing the slower etching hydrogen annealed nitrided silicon dioxide layer.
摘要翻译：已经开发了限定用于MOSFET器件的导电栅极结构的方法，其中导电栅极材料对下面的绝缘体层的蚀刻速率选择性被优化。在形成用于MOSFET栅极绝缘体层的氮化二氧化硅层之后，进行高温氢退火处理。高温退火程序用氢组分替代氮化二氧化硅栅极绝缘体层的顶部中的氮组分。当与非氢退火氮化二氧化硅对应物相比时，特定干蚀刻环境中的氢退火层的蚀刻速率现在降低。因此，当采用较慢的蚀刻氢退火氮化二氧化硅层时，导电栅极材料对底层栅极绝缘体材料的蚀刻速率选择性增加。

10. 发明授权

US07071066B2 Method and structure for forming high-k gates 失效
标题翻译：用于形成高k门的方法和结构
公开(公告)号：US07071066B2
公开(公告)日：2006-07-04
申请号：US10662845
申请日：2003-09-15
申请人： Ming-Fang Wang , Chia-Lin Chen , Chih-Wei Yang , Chi-Chun Chen , Tuo-Hung Hou , Yeou-Ming Lin , Liang-Gi Yao , Shih-Chang Chen
发明人： Ming-Fang Wang , Chia-Lin Chen , Chih-Wei Yang , Chi-Chun Chen , Tuo-Hung Hou , Yeou-Ming Lin , Liang-Gi Yao , Shih-Chang Chen
IPC分类号： H01L21/336 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/517 , H01L21/28185 , H01L21/28194 , H01L21/3141 , H01L29/513
摘要： A method for forming an improved gate stack structure having improved electrical properties in a gate structure forming process A method for forming a high dielectric constant gate structure including providing a silicon substrate comprising exposed surface portions; forming an interfacial layer over the exposed surface portions having a thickness of less than about 10 Angstroms; forming a high dielectric constant metal oxide layer over the interfacial layer having a dielectric constant of greater than about 10; forming a barrier layer over the high dielectric constant metal oxide layer; forming an electrode layer over the barrier layer; and, etching according to an etching pattern through a thickness of the electrode layer, barrier layer, high dielectric constant material layer, and the interfacial layer to form a high dielectric constant gate structure.
摘要翻译：一种用于形成在栅极结构形成工艺中具有改进的电性能的改进的栅极堆叠结构的方法用于形成高介电常数栅极结构的方法，包括提供包括暴露表面部分的硅衬底; 在暴露的表面部分上形成具有小于约10埃的厚度的界面层; 在介电常数大于约10的界面层上形成高介电常数金属氧化物层; 在高介电常数金属氧化物层上形成阻挡层; 在阻挡层上形成电极层; 并且根据蚀刻图案通过电极层，阻挡层，高介电常数材料层和界面层的厚度进行蚀刻，以形成高介电常数栅极结构。

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