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1. 发明授权

US08110490B2 Gate oxide leakage reduction 有权
标题翻译：栅极氧化物泄漏减少
公开(公告)号：US08110490B2
公开(公告)日：2012-02-07
申请号：US11839399
申请日：2007-08-15
申请人： Matt Yeh , Da-Yuan Lee , Chi-Chun Chen , Hun-Jan Tao
发明人： Matt Yeh , Da-Yuan Lee , Chi-Chun Chen , Hun-Jan Tao
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28202 , H01L21/28185 , H01L29/518 , H01L29/78
摘要： A method of manufacturing a semiconductor device comprising forming a gate oxide layer over a substrate subjecting the gate oxide layer to a first nitridation process, subjecting the gate oxide layer to a first anneal process after the first nitridation process, subjecting the gate oxide layer to a second nitridation process after the first anneal process, subjecting the gate oxide layer to a second anneal process after the second nitridation process, and forming a gate electrode over the gate oxide.
摘要翻译：一种制造半导体器件的方法，包括在使栅极氧化层进行第一氮化处理的衬底上形成栅极氧化层，在第一次氮化处理之后对栅极氧化物层进行第一退火处理，对栅极氧化物层进行在第一退火处理之后的第二次氮化处理，在第二次氮化处理之后对栅极氧化物层进行第二退火处理，并在栅极氧化物上形成栅电极。

2. 发明申请

US20090047799A1 GATE OXIDE LEAKAGE REDUCTION 有权
标题翻译：栅氧化物泄漏减少
公开(公告)号：US20090047799A1
公开(公告)日：2009-02-19
申请号：US11839399
申请日：2007-08-15
申请人： Matt Yeh , Da-Yuan Lee , Chi-Chun Chen , Hun-Jan Tao
发明人： Matt Yeh , Da-Yuan Lee , Chi-Chun Chen , Hun-Jan Tao
IPC分类号： H01L21/324 , H01L29/78
CPC分类号： H01L21/28202 , H01L21/28185 , H01L29/518 , H01L29/78
摘要： A method of manufacturing a semiconductor device comprising forming a gate oxide layer over a substrate subjecting the gate oxide layer to a first nitridation process, subjecting the gate oxide layer to a first anneal process after the first nitridation process, subjecting the gate oxide layer to a second nitridation process after the first anneal process, subjecting the gate oxide layer to a second anneal process after the second nitridation process, and forming a gate electrode over the gate oxide.
摘要翻译：一种制造半导体器件的方法，包括在使栅极氧化层进行第一氮化处理的衬底上形成栅极氧化层，在第一次氮化处理之后对栅极氧化物层进行第一退火处理，对栅极氧化物层进行在第一退火处理之后的第二次氮化处理，在第二次氮化处理之后对栅极氧化物层进行第二退火处理，并在栅极氧化物上形成栅电极。

3. 发明授权

US08222132B2 Fabricating high-K/metal gate devices in a gate last process 有权
标题翻译：在最后一道工序中制造高K /金属栅极器件
公开(公告)号：US08222132B2
公开(公告)日：2012-07-17
申请号：US12567227
申请日：2009-09-25
申请人： Da-Yuan Lee , Jian-Hao Chen , Chi-Chun Chen , Matt Yeh , Hsing-Jui Lee
发明人： Da-Yuan Lee , Jian-Hao Chen , Chi-Chun Chen , Matt Yeh , Hsing-Jui Lee
IPC分类号： H01L21/3205
CPC分类号： H01L21/823814 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L29/7848
摘要： The present disclosure provides a method that includes forming first and second gate structures over first and second regions, respectively, removing a first dummy gate and first dummy dielectric from the first gate structure thereby forming a first trench and removing a second dummy gate and second dummy dielectric from the second gate structure thereby forming a second trench, forming a gate layer to partially fill the first and second trenches, forming a material layer to fill the remainder of the first and second trenches, removing a portion of the material layer such that a remaining portion of the material layer protects a first portion of the gate layer located at a bottom portion of the first and second trenches, removing a second portion of the gate layer, removing the remaining portion of the material layer from the first and second trenches.
摘要翻译：本公开提供了一种方法，其包括分别在第一和第二区域上形成第一和第二栅极结构，从第一栅极结构去除第一伪栅极和第一虚设电介质，从而形成第一沟槽并且去除第二虚拟栅极和第二虚拟栅极从第二栅极结构的电介质，从而形成第二沟槽，形成栅极层以部分地填充第一和第二沟槽，形成材料层以填充第一和第二沟槽的其余部分，去除材料层的一部分，使得材料层的剩余部分保护位于第一和第二沟槽的底部的栅极层的第一部分，去除栅极层的第二部分，从第一和第二沟槽去除材料层的剩余部分。

4. 发明申请

US20080096394A1 GATE DIELECTRIC LAYERS AND METHODS OF FABRICATING GATE DIELECTRIC LAYERS 有权
标题翻译：门电介质层和制造栅介质层的方法
公开(公告)号：US20080096394A1
公开(公告)日：2008-04-24
申请号：US11551577
申请日：2006-10-20
申请人： Chi-Chun Chen , Matt Yeh , Shih-Chang Chen , Mong-Song Liang , Jennifer Chen , Da-Yuan Lee
发明人： Chi-Chun Chen , Matt Yeh , Shih-Chang Chen , Mong-Song Liang , Jennifer Chen , Da-Yuan Lee
IPC分类号： H01L21/31
CPC分类号： H01L21/31155 , H01L21/02126 , H01L21/02211 , H01L21/02238 , H01L21/02255 , H01L21/02271 , H01L21/02321 , H01L21/0234 , H01L21/02351 , H01L21/26506 , H01L21/28185 , H01L21/2822 , H01L21/3141 , H01L21/31633 , H01L21/31662 , H01L21/823462
摘要： A method of forming a gate dielectric layer includes forming a gate dielectric layer over a substrate. The gate dielectric layer is processed with carbon-containing ions. The gate dielectric layer is thermally processed, thereby providing the gate dielectric layer with a level of carbon between about 1 atomic % and about 20 atomic %.
摘要翻译：形成栅极电介质层的方法包括在衬底上形成栅极电介质层。用含碳离子处理栅介质层。栅极电介质层被热处理，从而为栅极电介质层提供约1原子％至约20原子％之间的碳含量。

5. 发明申请

US20060275975A1 Nitridated gate dielectric layer 审中-公开
标题翻译：氮化栅介质层
公开(公告)号：US20060275975A1
公开(公告)日：2006-12-07
申请号：US11142488
申请日：2005-06-01
申请人： Matt Yeh , Da-Yuan Lee , Chi-Chun Chen , Jin Ying , Shih-Chang Chen
发明人： Matt Yeh , Da-Yuan Lee , Chi-Chun Chen , Jin Ying , Shih-Chang Chen
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823842 , H01L29/785
摘要： A metal-oxide-semiconductor field-effect transistors (MOSFET) with a gate structure having a deuterated layer is provided. In accordance with embodiments of the present invention, a transistor comprises the deuterated layer formed over a gate dielectric layer. A gate electrode is formed over the deuterated layer. The deuterated layer prevents or reduces dopant penetration into a substrate from the gate electrode. The deuterated layer may be, for example, formed by a thermal process in an ambient of a deuterated gas, such as deuterated ammonia. The deuterated layer may also be formed by a nitridation process using deuterated ammonia.
摘要翻译：提供具有氘代层的栅极结构的金属氧化物半导体场效应晶体管（MOSFET）。根据本发明的实施例，晶体管包括在栅介电层上形成的氘化层。在氘化层上形成栅电极。氘化层防止或减少掺杂剂从栅电极渗透到衬底中。氘化层可以例如通过氘化气体的环境中的热过程形成，例如氘代氨。氘化层也可以通过使用氘代氨的氮化方法形成。

6. 发明申请

US20100124818A1 FABRICATING HIGH-K/METAL GATE DEVICES IN A GATE LAST PROCESS 有权
标题翻译：在门过程中制造高K /金属门装置
公开(公告)号：US20100124818A1
公开(公告)日：2010-05-20
申请号：US12567227
申请日：2009-09-25
申请人： Da-Yuan Lee , Jian-Hao Chen , Chi-Chun Chen , Matt Yeh , Hsing-Jui Lee
发明人： Da-Yuan Lee , Jian-Hao Chen , Chi-Chun Chen , Matt Yeh , Hsing-Jui Lee
IPC分类号： H01L21/8234
CPC分类号： H01L21/823814 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L29/7848
摘要： The present disclosure provides a method that includes forming first and second gate structures over first and second regions, respectively, removing a first dummy gate and first dummy dielectric from the first gate structure thereby forming a first trench and removing a second dummy gate and second dummy dielectric from the second gate structure thereby forming a second trench, forming a gate layer to partially fill the first and second trenches, forming a material layer to fill the remainder of the first and second trenches, removing a portion of the material layer such that a remaining portion of the material layer protects a first portion of the gate layer located at a bottom portion of the first and second trenches, removing a second portion of the gate layer, removing the remaining portion of the material layer from the first and second trenches.
摘要翻译：本公开提供了一种方法，其包括分别在第一和第二区域上形成第一和第二栅极结构，从第一栅极结构去除第一伪栅极和第一虚设电介质，从而形成第一沟槽并且去除第二虚拟栅极和第二虚拟栅极从第二栅极结构的电介质，从而形成第二沟槽，形成栅极层以部分地填充第一和第二沟槽，形成材料层以填充第一和第二沟槽的其余部分，去除材料层的一部分，使得材料层的剩余部分保护位于第一和第二沟槽的底部的栅极层的第一部分，去除栅极层的第二部分，从第一和第二沟槽去除材料层的剩余部分。

7. 发明授权

US07713854B2 Gate dielectric layers and methods of fabricating gate dielectric layers 有权
标题翻译：栅极电介质层和制造栅极电介质层的方法
公开(公告)号：US07713854B2
公开(公告)日：2010-05-11
申请号：US11551577
申请日：2006-10-20
申请人： Chi-Chun Chen , Matt Yeh , Shih-Chang Chen , Mong-Song Liang , Jennifer Chen , Da-Yuan Lee
发明人： Chi-Chun Chen , Matt Yeh , Shih-Chang Chen , Mong-Song Liang , Jennifer Chen , Da-Yuan Lee
IPC分类号： H01L21/3205
CPC分类号： H01L21/31155 , H01L21/02126 , H01L21/02211 , H01L21/02238 , H01L21/02255 , H01L21/02271 , H01L21/02321 , H01L21/0234 , H01L21/02351 , H01L21/26506 , H01L21/28185 , H01L21/2822 , H01L21/3141 , H01L21/31633 , H01L21/31662 , H01L21/823462
摘要： A method of forming a gate dielectric layer includes forming a gate dielectric layer over a substrate. The gate dielectric layer is processed with carbon-containing ions. The gate dielectric layer is thermally processed, thereby providing the gate dielectric layer with a level of carbon between about 1 atomic % and about 20 atomic %.
摘要翻译：形成栅极电介质层的方法包括在衬底上形成栅极电介质层。用含碳离子处理栅介质层。栅极电介质层被热处理，从而为栅极电介质层提供约1原子％至约20原子％之间的碳含量。

8. 发明授权

US07629275B2 Multiple-time flash anneal process 有权
标题翻译：多次闪光退火工艺
公开(公告)号：US07629275B2
公开(公告)日：2009-12-08
申请号：US11698239
申请日：2007-01-25
申请人： Jennifer Chen , Chi-Chun Chen , Hun-Jan Tao
发明人： Jennifer Chen , Chi-Chun Chen , Hun-Jan Tao
IPC分类号： H01L21/00
CPC分类号： H01L21/324 , H01L21/26513 , H01L21/2686 , H01L29/6659
摘要： A method of forming an integrated circuit is provided. The method includes performing a multiple-time flash anneal process to a wafer, wherein the multiple-time flash anneal process comprises preheating the wafer to a first preheat temperature; performing a first flash on the wafer with a first flash energy; preheating the wafer to a second preheat temperature; and performing a second flash on the wafer with a second flash energy.
摘要翻译：提供一种形成集成电路的方法。该方法包括对晶片执行多次闪光退火处理，其中多次闪光退火工艺包括将晶片预热至第一预热温度; 以第一闪光能量在晶片上进行第一次闪光; 将晶片预热至第二预热温度; 以及以第二闪光能量在所述晶片上执行第二次闪光。

9. 发明申请

US20080182430A1 Multiple-time flash anneal process 有权
标题翻译：多次闪光退火工艺
公开(公告)号：US20080182430A1
公开(公告)日：2008-07-31
申请号：US11698239
申请日：2007-01-25
申请人： Jennifer Chen , Chi-Chun Chen , Hun-Jan Tao
发明人： Jennifer Chen , Chi-Chun Chen , Hun-Jan Tao
IPC分类号： H01L21/00
CPC分类号： H01L21/324 , H01L21/26513 , H01L21/2686 , H01L29/6659
摘要： A method of forming an integrated circuit is provided. The method includes performing a multiple-time flash anneal process to a wafer, wherein the multiple-time flash anneal process comprises preheating the wafer to a first preheat temperature; performing a first flash on the wafer with a first flash energy; preheating the wafer to a second preheat temperature; and performing a second flash on the wafer with a second flash energy.
摘要翻译：提供一种形成集成电路的方法。该方法包括对晶片执行多次闪光退火处理，其中多次闪光退火工艺包括将晶片预热至第一预热温度; 以第一闪光能量在晶片上进行第一次闪光; 将晶片预热至第二预热温度; 以及以第二闪光能量在所述晶片上执行第二次闪光。

10. 发明申请

US20110117734A1 Method of Fabricating High-K Poly Gate Device 审中-公开
标题翻译：制造高K多栅极器件的方法
公开(公告)号：US20110117734A1
公开(公告)日：2011-05-19
申请号：US13014548
申请日：2011-01-26
申请人： Da-Yuan Lee , Chien-Hao Huang , Chi-Chun Chen , Kang-Cheng Lin
发明人： Da-Yuan Lee , Chien-Hao Huang , Chi-Chun Chen , Kang-Cheng Lin
IPC分类号： H01L21/28
CPC分类号： H01L29/513 , H01L21/823828 , H01L29/4966 , H01L29/518
摘要： The present disclosure provides a semiconductor device that includes a semiconductor substrate, and a transistor formed in the substrate. The transistor has a gate structure that includes an interfacial layer formed on the substrate, a high-k dielectric layer formed on the interfacial layer, a capping layer formed on the high-k dielectric layer, the capping layer including a silicon oxide, silicon oxynitride, silicon nitride, or combinations thereof, and a polysilicon layer formed on the capping layer.
摘要翻译：本公开提供了一种半导体器件，其包括半导体衬底和形成在衬底中的晶体管。晶体管具有栅极结构，该栅极结构包括形成在衬底上的界面层，形成在界面层上的高k电介质层，形成在高k电介质层上的覆盖层，覆盖层包括氧化硅，氮氧化硅，氮化硅或其组合，以及形成在覆盖层上的多晶硅层。

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