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1. 发明授权

US06680957B1 Group III nitride compound semiconductor laser 失效
标题翻译： III族氮化物化合物半导体激光器
公开(公告)号：US06680957B1
公开(公告)日：2004-01-20
申请号：US09515493
申请日：2000-02-29
申请人： Masayoshi Koike , Shiro Yamasaki , Yuta Tezen , Seiji Nagai , Akira Kojima , Toshio Hiramatsu
发明人： Masayoshi Koike , Shiro Yamasaki , Yuta Tezen , Seiji Nagai , Akira Kojima , Toshio Hiramatsu
IPC分类号： H01S500
CPC分类号： B82Y20/00 , H01S5/22 , H01S5/34333
摘要： A semiconductor laser 101 comprises a sapphire substrate 1, an AlN buffer layer 2, Si-doped GaN n-layer 3, Si-doped Al0.1Ga0.9N n-cladding layer 4, Si-doped GaN n-guide layer 5, an active layer 6 having multiple quantum well (MQW) structure in which about 35 Å in thickness of GaN barrier layer 62 and about 35 Å in thickness of Ga0.95In0.05N well layer 61 are laminated alternately, Mg-doped GaN p-guide layer 7, Mg-doped Al0.1Ga0.9N p-cladding layer 8, and Mg-doped GaN p-contact layer 9 are formed successively thereon. A ridged hole injection part B which contacts to a ridged resonator part A is formed to have the same width as the width w of an Ni electrode 10. Holes transmitted from the Ni electrode 10 are injected to the active layer 6 with high current density, and electric current threshold for laser oscillation can be decreased. Electric current threshold can be improved more effectively by forming also the p-guide layer 7 to have the same width as the width w of the Ni electrode 10.
摘要翻译：半导体激光器101包括蓝宝石衬底1，AlN缓冲层2，掺杂Si的GaN n层3，掺杂Si的Al 0.1 Ga 0.9 N n包层4，掺杂Si的GaN n引导层5，具有多个量子阱（MQW）结构的有源层6，其中厚度约为35的GaN阻挡层62和约35厚度的Ga0.95In0.05N阱层61交替层叠，掺杂Mg的GaN p引导层如图7所示，依次形成Mg掺杂的Al 0.1 Ga 0.9 N p包覆层8和Mg掺杂的GaN p接触层9。与脊状谐振器部件A接触的脊状空穴注入部分B形成为具有与Ni电极10的宽度w相同的宽度。从Ni电极10传输的孔以高电流密度注入到有源层6中，可以降低激光振荡的电流阈值。也可以通过将p导向层7形成为具有与Ni电极10的宽度w相同的宽度来更有效地提高电流阈值。

2. 发明授权

US07491984B2 Method for fabricating group III nitride compound semiconductors and group III nitride compound semiconductor devices 失效
标题翻译：制备III族氮化物化合物半导体和III族氮化物化合物半导体器件的方法
公开(公告)号：US07491984B2
公开(公告)日：2009-02-17
申请号：US10978438
申请日：2004-11-02
申请人： Masayoshi Koike , Yuta Tezen , Toshio Hiramatsu , Seiji Nagai
发明人： Masayoshi Koike , Yuta Tezen , Toshio Hiramatsu , Seiji Nagai
IPC分类号： H01L21/00
CPC分类号： H01L33/007 , H01L21/0237 , H01L21/0242 , H01L21/02433 , H01L21/02458 , H01L21/0254 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L21/02631 , H01L21/02639 , H01L21/02647
摘要： The present invention provides a Group III nitride compound semiconductor with suppressed generation of threading dislocations.A GaN layer 31 is subjected to etching, so as to form an island-like structure having a shape of, for example, dot, stripe, or grid, thereby providing a trench/mesa structure, and a mask 4 is formed at the bottom of the trench such that the upper surface of the mask 4 is positioned below the top surface of the GaN layer 31. A GaN layer 32 is lateral-epitaxially grown with the top surface 31a of the mesa and sidewalls 31b of the trench serving as nuclei, to thereby bury the trench, and then epitaxial growth is effected in the vertical direction. In the upper region of the GaN layer 32 formed above the mask 4 through lateral epitaxial growth, propagation of threading dislocations contained in the GaN layer 31 can be prevented.
摘要翻译：本发明提供了具有抑制的穿透位错产生的III族氮化物化合物半导体。对GaN层31进行蚀刻，以形成具有例如点状，条状或格栅形状的岛状结构，由此提供沟槽/台面结构，并且在底部形成掩模4 使得掩模4的上表面位于GaN层31的顶表面之下。GaN层32被侧壁外延生长，台面的顶表面31a和用作核的沟槽的侧壁31b ，从而埋入沟槽，然后在垂直方向进行外延生长。在通过横向外延生长形成在掩模4上方的GaN层32的上部区域中，可以防止包含在GaN层31中的穿透位错的传播。

3. 发明申请

US20050093099A1 Method for fabricating group III nitride compound semiconductors and group III nitride compound semiconductor devices 失效
标题翻译：制备III族氮化物化合物半导体和III族氮化物化合物半导体器件的方法
公开(公告)号：US20050093099A1
公开(公告)日：2005-05-05
申请号：US10978438
申请日：2004-11-02
申请人： Masayoshi Koike , Yuta Tezen , Toshio Hiramatsu , Seiji Nagai
发明人： Masayoshi Koike , Yuta Tezen , Toshio Hiramatsu , Seiji Nagai
IPC分类号： H01L21/20 , H01L21/205 , H01L33/00 , H01L29/06 , C30B1/00 , H01L21/36 , H01L29/20 , H01L31/0304 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L33/007 , H01L21/0237 , H01L21/0242 , H01L21/02433 , H01L21/02458 , H01L21/0254 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L21/02631 , H01L21/02639 , H01L21/02647
摘要： The present invention provides a Group III nitride compound semiconductor with suppressed generation of threading dislocations. A GaN layer 31 is subjected to etching, so as to form an island-like structure having a shape of, for example, dot, stripe, or grid, thereby providing a trench/mesa structure, and a mask 4 is formed at the bottom of the trench such that the upper surface of the mask 4 is positioned below the top surface of the GaN layer 31. A GaN layer 32 is lateral-epitaxially grown with the top surface 31a of the mesa and sidewalls 31b of the trench serving as nuclei, to thereby bury the trench, and then epitaxial growth is effected in the vertical direction. In the upper region of the GaN layer 32 formed above the mask 4 through lateral epitaxial growth, propagation of threading dislocations contained in the GaN layer 31 can be prevented.
摘要翻译：本发明提供了具有抑制的穿透位错产生的III族氮化物化合物半导体。对GaN层31进行蚀刻，以形成具有例如点状，条状或格栅形状的岛状结构，由此提供沟槽/台面结构，并且在底部形成掩模4 使得掩模4的上表面位于GaN层31的顶表面下方。 GaN层32与作为核的沟槽的台面的顶面31a和侧壁31b进行横向外延生长，从而埋入沟槽，然后沿垂直方向进行外延生长。在通过横向外延生长形成在掩模4上方的GaN层32的上部区域中，可以防止包含在GaN层31中的穿透位错的传播。

4. 发明授权

US07141444B2 Production method of III nitride compound semiconductor and III nitride compound semiconductor element 失效
公开(公告)号：US07141444B2
公开(公告)日：2006-11-28
申请号：US10221486
申请日：2001-03-12
申请人： Masayoshi Koike , Yuta Tezen , Hiroshi Yamashita , Seiji Nagai , Toshio Hiramatsu
发明人： Masayoshi Koike , Yuta Tezen , Hiroshi Yamashita , Seiji Nagai , Toshio Hiramatsu
IPC分类号： H01L21/00
CPC分类号： H01L21/0265 , H01L21/0237 , H01L21/0242 , H01L21/02433 , H01L21/02458 , H01L21/02505 , H01L21/0254 , H01L21/0262 , H01L21/02639 , H01L21/02645 , H01L21/02647
摘要： A first Group III nitride compound semiconductor layer 31 is etched, to thereby form an island-like structure such as a dot-like, stripe-shaped, or grid-like structure, so as to provide a trench/mesa such that layer different from the first Group III nitride compound semiconductor layer 31 is exposed at the bottom portion of the trench. Thus, a second Group III nitride compound layer 32 can be epitaxially grown, laterally, with a top surface of the mesa and a sidewall/sidewalls of the trench serving as a nucleus, to thereby bury the trench and also grow the layer in the vertical direction. In this case, propagation of threading dislocations contained in the first Group III nitride compound semiconductor layer 31 can be prevented in the upper portion of the second Group III nitride compound semiconductor 32 that is formed through lateral epitaxial growth. Etching may be performed until a cavity portion is provided in the substrate. The layer serving as a nucleus of ELO may be doped with indium (In) having an atomic radius greater than that of gallium (Ga) serving as a predominant element. The first semiconductor layer may be a multi-component layer containing a plurality of numbers of repetitions of a unit of a buffer layer and a single-crystal layer.

5. 发明授权

US06861305B2 Methods for fabricating group III nitride compound semiconductors and group III nitride compound semiconductor devices 失效
标题翻译：制备III族氮化物化合物半导体和III族氮化物化合物半导体器件的方法
公开(公告)号：US06861305B2
公开(公告)日：2005-03-01
申请号：US10240249
申请日：2001-03-29
申请人： Masayoshi Koike , Yuta Tezen , Toshio Hiramatsu , Seiji Nagai
发明人： Masayoshi Koike , Yuta Tezen , Toshio Hiramatsu , Seiji Nagai
IPC分类号： H01L21/20 , H01L21/205 , H01L33/00 , H01L21/8238
CPC分类号： H01L33/007 , H01L21/0237 , H01L21/0242 , H01L21/02433 , H01L21/02458 , H01L21/0254 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L21/02631 , H01L21/02639 , H01L21/02647
摘要： The present invention provides a Group III nitride compound semiconductor with suppressed generation of threading dislocations. A GaN layer 31 is subjected to etching, so as to form an island-like structure having a shape of, for example, dot, strip, or grid, thereby providing a trench/mesa structure, and a mask 4 is formed at the bottom of the trench such that the upper surface of the mask 4 is positioned below the top surface of the GaN layer 31. A GaN layer 32 is lateral-epitaxially grown with the top surface 31a of the mesa and sidewalls 31b of the trench serving as nuclei, to thereby bury the trench, and then epitaxial growth is effected in the vertical direction. In the upper region of the GaN layer 32 formed above the mask 4 through lateral epitaxial growth, propagation of threading dislocations contained in the GaN layer is 31 can be prevented.
摘要翻译：本发明提供了具有抑制的穿透位错产生的III族氮化物化合物半导体。对GaN层31进行蚀刻，以形成例如点状，带状或栅格的形状的岛状结构，从而提供沟槽/台面结构，并且在底部形成掩模4 使得掩模4的上表面位于GaN层31的顶表面之下。GaN层32被侧壁外延生长，台面的顶表面31a和用作核的沟槽的侧壁31b ，从而埋入沟槽，然后在垂直方向进行外延生长。在通过横向外延生长在掩模4上方形成的GaN层32的上部区域中，可以防止包含在GaN层中的穿透位错的传播为31。

6. 发明授权

US06855620B2 Method for fabricating Group III nitride compound semiconductor substrates and semiconductor devices 有权
标题翻译：制备III族氮化物化合物半导体衬底和半导体器件的方法
公开(公告)号：US06855620B2
公开(公告)日：2005-02-15
申请号：US10258546
申请日：2001-03-02
申请人： Masayoshi Koike , Seiji Nagai , Yuta Tezen
发明人： Masayoshi Koike , Seiji Nagai , Yuta Tezen
IPC分类号： C30B29/38 , H01L21/20 , H01L21/205 , H01L33/06 , H01L33/32 , H01S5/323 , H01S5/343 , H01L21/36 , H01L31/0336 , H01L31/3028
CPC分类号： H01L21/0254 , H01L21/0237 , H01L21/0242 , H01L21/02458 , H01L21/0262 , H01L21/02631 , H01L21/02639 , H01L21/0265 , H01L33/007 , H01L33/0075
摘要： A GaN layer 31 is subjected to etching, so as to form an island-like structure having, for example, a dot, stripe, or grid shape, thereby providing a trench/mesa structure including mesas and trenches whose bottoms sink into the surface of a substrate base 1. Subsequently, a GaN layer 32 is lateral-epitaxially grown with the top surfaces of the mesas and sidewalls of the trenches serving as nuclei, to thereby fill upper portions of the trenches (depressions of the substrate base 1), and then epitaxial growth is effected in the vertical direction. In this case, propagation of threading dislocations contained in the GaN layer 31 can be prevented in the upper portion of the GaN layer 32 that is formed through lateral epitaxial growth. Thereafter, the remaining GaN layer 31 is removed through etching, together with the GaN layer 32 formed atop the GaN layer 31, and subsequently, a GaN layer 33 is lateral-epitaxially grown with the top surfaces of mesas and sidewalls of trenches serving as nuclei, the mesas and trenches being formed of the remaining GaN layer 32, thereby producing a GaN substrate 30 in which threading dislocations are considerably suppressed. When the area of a portion of the GaN layer 31 at which the GaN substrate 30 is in contact with the substrate base 1 is reduced, separation of the GaN substrate 30 from the substrate base 1 is readily attained.
摘要翻译：对GaN层31进行蚀刻，以形成例如点状，条状或格子状的岛状结构，从而提供包括台面和沟槽的沟槽/台面结构，其底部沉入到接下来，GaN层32被横向外延生长，台阶的顶表面和沟槽的侧壁用作核，从而填充沟槽的上部（衬底1的凹陷），以及则在垂直方向进行外延生长。在这种情况下，在通过横向外延生长形成的GaN层32的上部可以防止包含在GaN层31中的穿透位错的传播。此后，残留的GaN层31与形成在GaN层31顶上的GaN层32一起通过蚀刻去除，随后，GaN层33被横向外延生长，作为用作核的沟槽的台面和侧壁的顶面，台面和沟槽由剩余的GaN层32形成，从而产生显着地抑制穿透位错的GaN衬底30。当GaN衬底30与衬底基底1接触的部分GaN层31的面积减小时，容易获得GaN衬底30与衬底基底1的分离。

7. 发明授权

US07052979B2 Production method for semiconductor crystal and semiconductor luminous element 有权
标题翻译：半导体晶体和半导体发光元件的制造方法
公开(公告)号：US07052979B2
公开(公告)日：2006-05-30
申请号：US10467566
申请日：2002-02-12
申请人： Seiji Nagai , Kazuyoshi Tomita , Shiro Yamazaki , Yuta Tezen , Toshio Hiramatsu
发明人： Seiji Nagai , Kazuyoshi Tomita , Shiro Yamazaki , Yuta Tezen , Toshio Hiramatsu
IPC分类号： H01L21/20
CPC分类号： C30B25/02 , C30B25/18 , C30B29/403 , C30B29/406 , H01L21/0237 , H01L21/02381 , H01L21/02458 , H01L21/0254 , H01L21/0262 , H01L21/02639 , H01L21/0265 , H01L33/0066 , H01L33/007
摘要： When a substrate layer (desired semiconductor crystal) made of a group III nitride compound is grown on a base substrate comprising a lot of projection parts, a cavity in which a semiconductor crystal is not deposited may be formed between each projection part although it depends on conditions such as the size of each projection part, arranging interval between each projection part and crystal growth. So when the thickness of the substrate layer is sufficiently larger compared with the height of the projection part, inner stress or outer stress become easier to act intensively to the projection part. As a result, such stress especially functions as shearing stress toward the projection part. When the shearing stress becomes larger, the projection part is ruptured. So utilizing the shearing stress enables to separate the base substrate and the substrate layer easily. The larger the cavities are formed, the more stress tends to concentrate to the projection parts, to thereby enable to separate the base substrate and the substrate layer more securely.
摘要翻译：当在包括大量投影部分的基底基板上生长由III族氮化物化合物制成的衬底层（期望的半导体晶体）时，可以在每个突出部分之间形成其中不沉积半导体晶体的空腔，尽管它取决于条件如每个投影部分的尺寸，每个投影部分之间的间隔和晶体生长。因此，当基板层的厚度与突出部分的高度相比足够大时，内应力或外应力变得更容易集中于投影部分。结果，这种应力特别地作用于朝向投影部分的剪切应力。当剪切应力变大时，突出部分破裂。因此，利用剪切应力使得能够容易地分离基底和基底层。形成空穴越大，应力越倾向于集中到突出部分，从而能够更牢固地分离基底基底和基底层。

8. 发明授权

US5953581A Methods for manufacturing group III nitride compound semiconductor laser diodes 失效
标题翻译：制造III族氮化物半导体激光二极管的方法
公开(公告)号：US5953581A
公开(公告)日：1999-09-14
申请号：US840895
申请日：1997-04-17
申请人： Shiro Yamasaki , Seiji Nagai , Masayoshi Koike
发明人： Shiro Yamasaki , Seiji Nagai , Masayoshi Koike
IPC分类号： H01L33/10 , H01L33/12 , H01L33/14 , H01L33/32 , H01S5/00 , H01S5/02 , H01S5/10 , H01S5/323 , H01S5/343 , H01L21/66
CPC分类号： H01S5/32308 , H01S5/0203
摘要： As a method for manufacturing a laser diode using a group III nitride compound semiconductor, independent dry etching process for forming electrodes and mirror facets are adopted. A portion of an upper semiconductor layer is etched for forming a window. An electrode for a lower semiconductor layer is formed through the window. After electrodes are formed, then, etching is carried out for forming mirror facets of laser cavity. This method realizes high oscillation, because the method enhances parallel and vertical degrees of the mirror facets. Further, cleanness of the mirror facets are improved, because they are formed after the electrodes are formed. The method further lowers resistivity of lower semiconductor layer, because its thickness can be controlled easily without etching excessively. As a result, luminous efficiency is improved.
摘要翻译：作为使用III族氮化物化合物半导体制造激光二极管的方法，采用用于形成电极和镜面的独立的干蚀刻工艺。上部半导体层的一部分被蚀刻以形成窗口。通过窗口形成下半导体层用电极。在形成电极之后，进行蚀刻以形成激光腔的镜面。该方法实现了高振荡，因为该方法增强了镜面的平行和垂直度。此外，改善了镜面的清洁度，因为它们在形成电极之后形成。该方法进一步降低下半导体层的电阻率，因为其厚度可以容易地控制，而不会过度蚀刻。结果，发光效率提高。

9. 发明授权

US06486068B2 Method for manufacturing group III nitride compound semiconductor laser diodes 失效
标题翻译：制造III族氮化物半导体激光二极管的方法
公开(公告)号：US06486068B2
公开(公告)日：2002-11-26
申请号：US09004608
申请日：1998-01-08
申请人： Shiro Yamasaki , Seiji Nagai , Masayoshi Koike , Isamu Akasaki , Hiroshi Amano , Isao Yamada , Jiro Matsuo
发明人： Shiro Yamasaki , Seiji Nagai , Masayoshi Koike , Isamu Akasaki , Hiroshi Amano , Isao Yamada , Jiro Matsuo
IPC分类号： H01L21302
CPC分类号： H01S5/0201 , H01S5/0203 , H01S5/32341
摘要： A method for manufacturing a laser diode using Group III nitride compound semiconductor comprising a buffer layer 2, an n+ layer 3, a cladding layer 4, an active layer 5, a p-type cladding layer 61, a contact layer 62, an SiO2 layer 9, an electrode 7 which is formed on the window formed in a portion of the SiO2 layer 9, and an electrode 8 which is formed on a portion of the n+ layer 3 by etching a portion of 4 layers from the contact layer 62 down to the cladding layer 4. One pair of opposite facets S of a cavity is formed by RIBE, and then the facets are etched by gas cluster ion beam etching using Ar gas. As a result, the facets S are flatted and the mirror reflection of the facets S is improved.
摘要翻译：一种使用III族氮化物化合物半导体制造激光二极管的方法，包括缓冲层2，n +层3，包覆层4，有源层5，p型覆层61，接触层62，SiO 2层如图9所示，形成在形成在SiO 2层9的一部分上的窗口上的电极7和通过从接触层62蚀刻4层的一部分而形成在n +层3的一部分上的电极8，通过RIBE形成空腔的一对相对面S，然后通过使用Ar气体的气体簇离子束蚀刻蚀刻该刻面。结果，小面S变平，并且小面S的镜面反射得到改善。

10. 发明授权

US06821800B2 Semiconductor light-emitting device and manufacturing method thereof 失效
标题翻译：半导体发光器件及其制造方法
公开(公告)号：US06821800B2
公开(公告)日：2004-11-23
申请号：US10326398
申请日：2002-12-23
申请人： Norikatsu Koide , Shinya Asami , Junichi Umezaki , Masayoshi Koike , Shiro Yamasaki , Seiji Nagai
发明人： Norikatsu Koide , Shinya Asami , Junichi Umezaki , Masayoshi Koike , Shiro Yamasaki , Seiji Nagai
IPC分类号： H01L2100
CPC分类号： H01L33/32 , B82Y20/00 , H01L29/155 , H01L33/06 , Y10S438/933
摘要： In a method of manufacturing a semiconductor light-emitting device involving the steps of: forming a first semiconductor layer; forming a light-emitting layer of superlattice structure by laminating a barrier layer being made of InY1Ga1-Y1N (Y1≧0) and a quantum well layer being made of InY2Ga1-Y2N (Y2>Y1 and Y2>0) on the first semiconductor layer; and forming a second semiconductor layer on the light-emitting layer, an uppermost barrier layer, which will become an uppermost layer of the light-emitting layer, is made thicker than the other barrier layers. Further, at the time of forming the second semiconductor layer, an upper surface of such uppermost barrier layer is caused to disappear so that the thickness of the uppermost barrier layer becomes substantially equal to those of the other barrier layers.
摘要翻译：在制造半导体发光器件的方法中，包括以下步骤：形成第一半导体层; 通过将由InY1Ga1-Y1N（Y1> = 0）构成的阻挡层和由InY2Ga1-Y2N（Y2> Y1和Y2> 0）构成的量子阱层层叠在第一半导体上形成超晶格结构的发光层层; 并且在发光层上形成第二半导体层，使作为发光层的最上层的最上层的阻挡层比其他阻挡层厚。此外，在形成第二半导体层时，使最上层势垒层的上表面消失，使得最上阻挡层的厚度变得基本上等于其它势垒层的厚度。

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