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1. 发明授权

US4799197A Semiconductor memory device having a CMOS sense amplifier 失效
标题翻译：具有CMOS读出放大器的半导体存储器件
公开(公告)号：US4799197A
公开(公告)日：1989-01-17
申请号：US91795
申请日：1987-09-01
申请人： Yukinori Kodama , Hirohiko Mochizuki , Masao Nakano , Tsuyoshi Ohira , Hidenori Nomura
发明人： Yukinori Kodama , Hirohiko Mochizuki , Masao Nakano , Tsuyoshi Ohira , Hidenori Nomura
IPC分类号： G11C11/401 , G11C7/10 , G11C7/18 , G11C11/409 , G11C11/4091 , G11C11/4097 , G11C7/00 , G11C11/24
CPC分类号： G11C11/4097 , G11C11/4091 , G11C7/1006 , G11C7/18
摘要： A semiconductor memory device comprises a memory cell array comprising memory cells; a plurality of pairs of bit lines which are coupled to the memory cells and a data bus, each bit line being divided into at least two pairs of bit line parts; at least one sense amplifier provided between the pairs of bit line parts in each of the pairs of bit lines, for sensing a difference in potential between bit line parts in each pair, the sense amplifier being formed with complementary metal oxide semiconductor transistors; and at least a pair of transfer gates provided between a non-data bus side and a data bus side of the sense amplifier, the pair of transfer gates being held in an off-state when the sense amplifier is activated.

2. 发明授权

US4870617A Semiconductor memory device having data bus reset circuits 失效
标题翻译：半导体存储器件具有数据总线复位电路
公开(公告)号：US4870617A
公开(公告)日：1989-09-26
申请号：US97558
申请日：1987-09-16
申请人： Masao Nakano , Tsuyoshi Ohira , Hirohiko Mochizuki , Yukinori Kodama , Hidenori Nomura
发明人： Masao Nakano , Tsuyoshi Ohira , Hirohiko Mochizuki , Yukinori Kodama , Hidenori Nomura
IPC分类号： G11C11/409 , G11C5/06 , G11C7/10 , G11C11/401
CPC分类号： G11C5/063 , G11C7/1048
摘要： A semiconductor memory device comprises a plurality of reset circuits connected to a data bus pair at different locations. Before each read operation, the reset circuits reset the data bus pair to a predetermined reset voltage. The resetting of the data bus pair is virtually unaffected by the distributed resistances and parasitic capacitances of the data bus pair, since the resetting is carried out at a plurality of locations on the data bus pair.
摘要翻译：半导体存储器件包括在不同位置连接到数据总线对的多个复位电路。在每次读取操作之前，复位电路将数据总线对复位到预定的复位电压。数据总线对的复位实际上不受数据总线对的分布电阻和寄生电容的影响，因为复位是在数据总线对上的多个位置进行的。

3. 发明授权

US4821232A Semiconductor memory device having data bus reset circuit 失效
标题翻译：具有数据总线复位电路的半导体存储器件
公开(公告)号：US4821232A
公开(公告)日：1989-04-11
申请号：US97556
申请日：1987-09-16
申请人： Masao Nakano , Tsuyoshi Ohira , Hirohiko Mochizuki , Yukinori Kodama , Hidenori Nomura
发明人： Masao Nakano , Tsuyoshi Ohira , Hirohiko Mochizuki , Yukinori Kodama , Hidenori Nomura
IPC分类号： G11C11/409 , G11C7/10 , G11C7/20 , G11C13/00 , G11C11/40
CPC分类号： G11C7/20 , G11C7/1048
摘要： A semiconductor memory device comprises a memory cell array comprising a plurality of memory cells arranged in a matrix arrangement, a sense amplifier, operatively connected to the memory cell array, amplifying a signal read out from one of the memory cells and having a pair of output terminals for outputting a complementary signal, a pair of data buses for transferring the complementary signal, a transfer gate for connecting the pair of output terminals to the pair of data buses responsive to a read operation, a data output buffer connected to the pair of data buses for outputting an output signal, and a reset circuit for resetting the pair of data buses to a predetermined voltage before each read operation responsive to a reset clock signal. The reset circuit comprises a first circuit connected to the pair of data buses for connecting the pair of data buses to a common node responsive to the reset clock signal, and a second circuit connected between the common node and a ground voltage for shifting a potential at the common node to a voltage which is the predetermined voltage greater than the ground voltage.
摘要翻译：半导体存储器件包括存储单元阵列，该存储单元阵列包括以矩阵布置的多个存储单元，读出放大器，可操作地连接到存储单元阵列，放大从一个存储单元读出的信号，并具有一对输出用于输出互补信号的端子，用于传送互补信号的一对数据总线，用于响应于读取操作将一对输出端连接到该对数据总线的传输门，连接到该对数据的数据输出缓冲器用于输出输出信号的总线;以及复位电路，用于响应于复位时钟信号在每次读取操作之前将该对数据总线复位到预定电压。复位电路包括连接到该对数据总线的第一电路，用于响应于复位时钟信号将一对数据总线连接到公共节点，以及连接在公共节点和接地电压之间的第二电路，该公共节点为大于接地电压的预定电压的电压。

4. 发明授权

US4807192A Memory device employing address multiplexing 失效
标题翻译：采用地址复用的存储器件
公开(公告)号：US4807192A
公开(公告)日：1989-02-21
申请号：US90988
申请日：1987-08-31
申请人： Masao Nakano , Hirohiko Mochizuki , Tsuyoshi Ohira , Yukinori Kodama , Hidenori Nomura
发明人： Masao Nakano , Hirohiko Mochizuki , Tsuyoshi Ohira , Yukinori Kodama , Hidenori Nomura
IPC分类号： G11C7/10 , G11C8/04 , G11C11/40 , G11C13/00
CPC分类号： G11C7/1018 , G11C8/04
摘要： A memory device employing address multiplexing comprises a counter. An external address is initially set in the counter and a counter address value is incremented responsive to toggle of a column address strobe. The counted address value in the counter is supplied as an address signal directly to a column decoder or indirectly to the column decoder through an address buffer. The memory device may be provided with a switching logic circuit which switches the address bits in the counter depending on switching information so that it is possible to arbitrarily determine which address bits in the counter are to determine a nibble address.

5. 发明授权

US4806795A Transfer gate circuit protected from latch up 失效
标题翻译：传输门电路防止锁定
公开(公告)号：US4806795A
公开(公告)日：1989-02-21
申请号：US97557
申请日：1987-09-16
申请人： Masao Nakano , Tsuyoshi Ohira , Hidenori Nomura
发明人： Masao Nakano , Tsuyoshi Ohira , Hidenori Nomura
IPC分类号： H01L27/08 , H01L21/8238 , H01L27/092 , H03K17/687 , H03K17/16 , H03K19/096
CPC分类号： H03K17/6872
摘要： A transfer gate circuit including a first MIS transistor which transmits an input signal supplied from an input side thereof to an output side thereof in accordance with a control signal supplied to a gate of the first MIS transistor; an inverter circuit connected between power supply lines which inverts the potential of the transmitted input signal; and an output level guarantee circuit comprising second and third MIS transistors which have conductivity type opposite to that of the first MIS transistor and are connected in series between one of the power supply lines and the output side, an output signal of the inverter circuit being supplied to a gate of the second MIS transistor, an inverted signal of the control signal supplied to the gate of the first MIS transistor being supplied to a gate of the third MIS transistor.
摘要翻译：一种传输门电路，包括：第一MIS晶体管，其根据提供给第一MIS晶体管的栅极的控制信号将从其输入侧提供的输入信号传输到其输出侧; 连接在电源线之间的逆变器电路，其反转所发送的输入信号的电位; 以及输出电平保证电路，包括第二和第三MIS晶体管，其具有与第一MIS晶体管的导电类型相反的导电类型，并且串联连接在一个电源线和输出侧之间，反相器电路的输出信号被提供到第二MIS晶体管的栅极，提供给第一MIS晶体管的栅极的控制信号的反相信号被提供给第三MIS晶体管的栅极。

6. 发明授权

US08544269B2 Engine 有权
标题翻译：发动机
公开(公告)号：US08544269B2
公开(公告)日：2013-10-01
申请号：US13122831
申请日：2009-09-17
申请人： Takeshi Takahashi , Hidenori Nomura , Kazuki Maetani , Terumitsu Takahata , Takao Kawabe , Kazuhiro Takenaka
发明人： Takeshi Takahashi , Hidenori Nomura , Kazuki Maetani , Terumitsu Takahata , Takao Kawabe , Kazuhiro Takenaka
IPC分类号： F02B33/44 , F02B33/00 , F02B37/00 , F02B37/013 , F02B37/18 , F02D23/00 , F02M25/07
CPC分类号： F02B37/013 , F02B29/0412 , F02B37/004 , F02B37/18 , F02B37/22 , F02B37/24 , F02B39/16 , F02B2037/122 , F02B2039/168 , F02D23/00 , F02D41/0007 , F02D2200/0406 , F02M26/08 , F02M26/47 , Y02T10/144 , Y02T10/146
摘要： An engine (100) provided with a variable series supercharging system (7) composed of a high-pressure supercharger (10) and a low-pressure supercharger (20), a supercharging pressure sensor (63) for detecting the pressure of intake air pressurized by the variable series supercharging system (7), a high-pressure supercharger rotation sensor (61) for detecting the rotational speed of the high-pressure supercharger (10), a variable actuator (14) for adjusting the capacity of the high-pressure supercharger (10), and a control device (60) capable of controlling the variable actuator (14). The control device (60) controls the variable actuator (14) based on detection signals from the supercharging pressure sensor (63) and the high-pressure supercharger rotation sensor (61).
摘要翻译：具有由高压增压器（10）和低压增压器（20）构成的可变串联增压系统（7）的发动机（100），用于检测加压的进气压力的增压压力传感器（63）通过变量串联增压系统（7），用于检测高压增压器（10）的转速的高压增压器旋转传感器（61），用于调节高压增压器（10）的容量的可变致动器（14）增压器（10）和能够控制可变致动器（14）的控制装置（60）。控制装置（60）基于来自增压压力传感器（63）和高压增压器旋转传感器（61）的检测信号来控制可变致动器（14）。

7. 发明申请

US20110138806A1 Engine 有权
标题翻译：发动机
公开(公告)号：US20110138806A1
公开(公告)日：2011-06-16
申请号：US13059209
申请日：2009-06-11
申请人： Takeshi Takahashi , Takao Kawabe , Hidenori Nomura , Tomoo Ogata , Kouji Shimizu , Satomi Ukai
发明人： Takeshi Takahashi , Takao Kawabe , Hidenori Nomura , Tomoo Ogata , Kouji Shimizu , Satomi Ukai
IPC分类号： F02D23/02
CPC分类号： F02D41/0007 , F02B37/004 , F02B37/013 , F02B37/18 , F02B2037/122 , F02B2039/168 , F02M26/05 , Y02T10/144
摘要： Turbines (21b, 31b) and compressors (21a, 31a), which constitute superchargers (21, 31), are disposed in series on an exhaust gas passage (3) and an air intake passage (2), respectively. The supercharger (31) is equipped with a supercharger rotation sensor (61), which transmits a detection signal obtained according to the rotation of the compressor (31a) to a control device, a bypass passage (4), which bypasses exhaust gas from the upstream side to the downstream side of the turbine (31b), and a bypass valve (34), which regulates the flow rate of exhaust gas flowing through the bypass passage (4). Control device (60) regulates the rotational speed of the compressors (21a, 31a) in a high-efficiency range by producing a control signal based on the detection signal from the supercharger rotation sensor (61), and sending the control signal to the bypass valve (34).
摘要翻译：构成增压器（21,31）的涡轮机（21b，31b）和压缩机（21a，31a）分别串联配置在排气通路（3）和进气通路（2）上。增压器（31）配备有增压器旋转传感器（61），其将根据压缩机（31a）的旋转获得的检测信号发送到控制装置，旁路通路（4），旁路通路（31b）的下游侧的上游侧和调节流经旁路通路（4）的废气的流量的旁通阀（34）。控制装置（60）通过基于来自增压器旋转传感器（61）的检测信号产生控制信号，在高效率范围内调节压缩机（21a，31a）的转速，并将控制信号发送到旁路阀（34）。

8. 发明授权

US4985868A Dynamic random access memory having improved refresh timing 失效
标题翻译：动态随机存取存储器具有改善的刷新时序
公开(公告)号：US4985868A
公开(公告)日：1991-01-15
申请号：US449427
申请日：1989-12-14
申请人： Tomio Nakano , Hidenori Nomura
发明人： Tomio Nakano , Hidenori Nomura
IPC分类号： G11C11/408 , G11C11/403 , G11C11/406 , G11C11/407
CPC分类号： G11C11/406
摘要： A dynamic random access memory including: a memory constituted by a plurality of dynamic type memory cells; a refresh control circuit for refreshing the memory cells by controlling a refresh address circuit in a refresh mode; an address latch circuit for latching an external address signal in a read/write mode and latching a refresh address signal in the refresh mode; a clock generating circuit for generating a second clock and a third clock based on a first clock obtained after a predetermined delay time from a trailing edge of a row address strobe signal, the second clock controlling a first timing for taking the external address signal into the address latch circuit in the read/write mode, and the third clock is generated after the second clock and controls a second timing for taking the refresh address signal into the address latch circuit in the refresh mode.

9. 发明授权

US07835851B2 Fuel injection system 失效
标题翻译：燃油喷射系统
公开(公告)号：US07835851B2
公开(公告)日：2010-11-16
申请号：US11908654
申请日：2005-11-10
申请人： Takafumi Teramoto , Takashi Miyamoto , Kazuhiro Yamada , Rio Takahashi , Hidenori Nomura , Yasurou Kimura
发明人： Takafumi Teramoto , Takashi Miyamoto , Kazuhiro Yamada , Rio Takahashi , Hidenori Nomura , Yasurou Kimura
IPC分类号： B60T7/12 , G06F19/00
CPC分类号： F02D41/407 , F02B3/06 , F02D17/04 , F02D41/0007 , F02D41/042 , F02D41/061 , F02D41/365 , F02M59/447 , Y02T10/44
摘要： There is well known that the more the timing of fuel injection is advanced, the more the start ability of an engine is improved. However, with regard to the conventional fuel injection system, when a stopping process of the engine is performed, a timer piston determining timing of fuel injection remains at a position at which the piston exists at the time that the stopping process is performed. Then, at the time of next starting of the engine, the timer piston does not often exist in the advanced angle side and the start ability may be poor. For solving this problem, an engine control module (ECM) 21 advances a timer piston 52 and stops fuel injection of a fuel injection pump 40 at the time that actual phase difference C reaches stopping target phase difference Z so as to stop an engine 20.
摘要翻译：众所周知，燃油喷射的时间越多，发动机的启动能力越好。然而，关于传统的燃料喷射系统，当执行发动机的停止过程时，定时器活塞确定燃料喷射定时保持在执行停止处理时存在活塞的位置。然后，在发动机的下一次起动时，定时器活塞并不经常存在于提前角侧，起动能力可能较差。为了解决这个问题，发动机控制模块（ECM）21推进定时器活塞52，并且在实际相位差C达到停止目标相位差Z时停止燃料喷射泵40的燃料喷射以停止发动机20。

10. 发明授权

US5909407A Word line multi-selection circuit for a memory device 失效
标题翻译：用于存储器件的字线多选电路
公开(公告)号：US5909407A
公开(公告)日：1999-06-01
申请号：US30269
申请日：1998-02-25
申请人： Yasuhiro Yamamoto , Takaaki Furuyama , Hidenori Nomura
发明人： Yasuhiro Yamamoto , Takaaki Furuyama , Hidenori Nomura
IPC分类号： G11C11/41 , G11C8/00 , G11C11/407 , G11C11/408 , G11C11/4096
CPC分类号： G11C8/00 , G11C11/408 , G11C11/4096
摘要： A semiconductor memory device, such as a DRAM, includes a word line multi-selection circuit. A row decoder generates a word line selecting signal for selecting a read-out word line for use in the current cycle to read information from a selected memory cell. The word line selecting signal is also used to select a write-back word line which was used in the previous cycle to read cell information and is used in the current cycle to write back cell information. The word line multi-selection circuit includes a register for temporarily storing the cell information read from the selected memory cell and also for providing, in the current cycle, information read in the previous cycle in order to perform the write-back operation.
摘要翻译：诸如DRAM的半导体存储器件包括字线多选电路。行解码器生成用于选择用于当前周期的读出字线的字线选择信号以从所选存储单元读取信息。字线选择信号也用于选择在前一周期中使用的写回字线来读取单元信息，并在当前周期中用于写入单元信息。字线多选电路包括用于临时存储从所选择的存储单元读取的单元信息的寄存器，并且还用于在当前周期中提供在前一周期中读取的信息，以执行回写操作。

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