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1. 发明授权

US4338510A Electrode type steam vaporizer having corrosion resistant nickel ferrite electrodes and a protective cover 失效
标题翻译：具有耐腐蚀镍铁氧体电极和保护罩的电极型蒸汽蒸发器
公开(公告)号：US4338510A
公开(公告)日：1982-07-06
申请号：US878787
申请日：1978-02-17
申请人： Masao Chihara , Shigeo Araki , Kazuhiko Asakawa
发明人： Masao Chihara , Shigeo Araki , Kazuhiko Asakawa
IPC分类号： H05B3/03 , F22B1/30 , F24F6/02 , H05B3/60
CPC分类号： F24F6/025 , F22B1/30
摘要： An electrode type steam vaporizer device is disclosed which includes a plurality of ferrite electrodes positioned in a water receptacle wherein AC voltage is applied to the electrodes thereby vaporizing water in the receptacle. Each of the ferrite electrodes is a sintered body made of a mixture of iron oxide and a divalent nickel oxide. The ferrite electrodes are contained in an electrode assembly located within the body of the water receptacle such that a pair of electrode terminals extend through the top wall of the receptacle. A cover having a power source connector receiving concavity in its surface is positioned on top on the water receptacle. The cover is rotatable between a first position where the concavity is in registry with the electrode terminals and a second position where the concavity is out of registry with the terminals. A power source connector is received in the concavity and is connectable with the electrode terminals only when the cover is in the first position. When the connector is attached to the device, the cover is trapped between the body of the water receptacle and the connector, thereby preventing the removal of the cover. Thus the receptacle may not be filled and the electrodes may not be cleaned unless the power connector is removed from the electrode terminals. Additionally, when not in use, the cover may be rotated to the second position whereby the electrode terminals are protected from dust accumulation.
摘要翻译：公开了一种电极型蒸汽蒸发器装置，其包括位于水容器中的多个铁氧体电极，其中AC电压施加到电极，从而蒸发容器中的水。每个铁氧体电极是由氧化铁和二价氧化镍的混合物制成的烧结体。铁氧体电极被包含在位于水容器主体内的电极组件中，使得一对电极端子延伸穿过容器的顶壁。具有在其表面上接收凹部的电源连接器的盖子位于水容器的顶部。盖可以在凹部与电极端子对准的第一位置和凹部不与端子对准的第二位置之间旋转。电源连接器被容纳在凹部中，并且仅当盖处于第一位置时才能与电极端子连接。当连接器连接到设备时，盖被捕获在水插座的主体和连接器之间，从而防止盖的移除。因此，插座可能不被填充，并且电极可能不被清洁，除非电源连接器从电极端子移除。此外，当不使用时，盖可以旋转到第二位置，由此保护电极端子免受灰尘积聚。

2. 发明授权

US06933238B2 Method for manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06933238B2
公开(公告)日：2005-08-23
申请号：US10748279
申请日：2003-12-31
申请人： Kazuhiko Asakawa
发明人： Kazuhiko Asakawa
IPC分类号： H01L21/76 , H01L21/762 , H01L21/311
CPC分类号： H01L21/76224
摘要： A method for manufacturing a semiconductor element of the present invention includes the steps of: forming, on a substrate, a protection oxide film, a nitride film, an insulation film for protecting the nitride film; forming a trench; etching the insulation film to widen its aperture toward an active region; forming a thermal oxidation film inside the trench; etching the nitride film using the insulation film as a mask to slide a step defined by the thermal oxidation film and the nitride film from an upper edge of the trench toward the active region; forming a filling oxide film; exposing the nitride film; etching the filling oxide film; and removing the nitride oxide film and the protection oxide film.
摘要翻译：本发明的半导体元件的制造方法包括以下步骤：在基板上形成保护氧化膜，氮化膜，保护氮化膜的绝缘膜; 形成沟槽; 蚀刻绝缘膜以将其孔径扩大到有源区域; 在沟槽内形成热氧化膜; 使用所述绝缘膜作为掩模蚀刻所述氮化物膜，以将所述热氧化膜和所述氮化物膜限定的步骤从所述沟槽的上边缘向所述有源区域滑动; 形成填充氧化膜; 曝光氮化膜; 蚀刻填充氧化膜; 并除去氮氧化物膜和保护氧化膜。

3. 发明申请

US20050080506A1 Method of determining remaining film thickness in polishing process 失效
标题翻译：在抛光过程中确定剩余膜厚度的方法
公开(公告)号：US20050080506A1
公开(公告)日：2005-04-14
申请号：US10768076
申请日：2004-02-02
申请人： Kazuhiko Asakawa
发明人： Kazuhiko Asakawa
IPC分类号： H01L21/66 , H01L21/304 , H01L21/76 , G06F19/00
CPC分类号： H01L22/26
摘要： The present invention of a method of determining remaining film thickness in polishing process can provide a technology for controlling a polishing amount of CMP in a device isolating process with satisfactory accuracy regardless of the ratio between the area of each of device forming regions and that of each of trench regions, the type of abrasive, etc.
摘要翻译：在抛光工艺中确定剩余膜厚度的方法的本发明可以提供一种用于在器件隔离工艺中以令人满意的精度控制CMP的抛光量的技术，而不管每个器件形成区域的面积与每个器件形成区域的面积之比沟槽区域，磨料类型等

4. 发明授权

US07737547B2 Dummy buried contacts and vias for improving contact via resistance in a semiconductor device 失效
标题翻译：用于通过半导体器件中的电阻改善接触的虚拟埋入触点和通孔
公开(公告)号：US07737547B2
公开(公告)日：2010-06-15
申请号：US11477522
申请日：2006-06-30
申请人： Kazuhiko Asakawa
发明人： Kazuhiko Asakawa
IPC分类号： H01L23/12
CPC分类号： H01L23/5226 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate having a plurality of conductive layers. The device further includes buried contacts and buried vias, which connect the interconnect layers respectively. At least one of the contacts and vias are dummy contacts and dummy vias.
摘要翻译：半导体器件包括具有多个导电层的半导体衬底。该器件还包括分别连接互连层的掩埋触点和埋入通孔。触点和通孔中的至少一个是虚拟触点和虚拟通孔。

5. 发明授权

US07018926B2 Method of manufacturing semiconductor device 失效
公开(公告)号：US07018926B2
公开(公告)日：2006-03-28
申请号：US10366442
申请日：2003-02-14
申请人： Kazuhiko Asakawa
发明人： Kazuhiko Asakawa
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/304
摘要： A method of manufacturing a semiconductor device includes a providing step and a polishing step. In the providing step, a semiconductor wafer is provided. The semiconductor wafer has a plane area including a plane surface and a peripheral area surrounding the plane area. The peripheral area has a hemispherical surface extending from the plane surface to a wafer end. The distance from an end of the plane surface to the wafer end is about 800–1000 μm. In the polishing step, mechanically and chemically polishing is conducted using a polishing pad with a polishing slurry.

6. 发明授权

US06787886B1 Semiconductor device and methods of fabricating the same 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US06787886B1
公开(公告)日：2004-09-07
申请号：US09497499
申请日：2000-02-04
申请人： Kazuhiko Asakawa , Wataru Shimizu
发明人： Kazuhiko Asakawa , Wataru Shimizu
IPC分类号： H01L2906
CPC分类号： H01L21/76897 , H01L21/76801 , H01L21/76802 , H01L21/76825 , H01L23/3192 , H01L23/5258 , H01L27/10808 , H01L27/10873 , H01L2924/0002 , H01L2924/19041 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate which has a major surface and a MOS transistor which has a gate and first and second diffusion regions and which is formed on the major surface. The semiconductor device also includes a laminated structure of a SOG layer, wherein the laminated structure is composed of a base layer and a surface layer formed on the base layer and is formed over the MOS transistor and wherein the surface layer is denser than the base layer.
摘要翻译：半导体器件包括具有主表面的半导体衬底和具有栅极和第一和第二扩散区域并且形成在主表面上的MOS晶体管。半导体器件还包括SOG层的层叠结构，其中层叠结构由基底层和形成在基底层上的表面层组成并形成在MOS晶体管上，并且其中表面层比基底层更致密。

7. 发明申请

US20060270249A1 Semiconductor device and method of fabricating the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060270249A1
公开(公告)日：2006-11-30
申请号：US11500951
申请日：2006-08-09
申请人： Kazuhiko Asakawa , Wataru Shimizu
发明人： Kazuhiko Asakawa , Wataru Shimizu
IPC分类号： H01L23/58 , H01L21/31
CPC分类号： H01L21/76897 , H01L21/76801 , H01L21/76802 , H01L21/76825 , H01L23/3192 , H01L23/5258 , H01L27/10808 , H01L27/10873 , H01L2924/0002 , H01L2924/19041 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate which has a major surface, and a MOS transistor which has a gate and first and second diffusion regions and which is formed on the major surface. The semiconductor device also includes a laminated structure of an SOG layer, wherein the laminated structure is composed of a base layer and a surface layer formed on the base layer. The laminated structure is formed over the MOS transistor, and the surface layer is denser than the base layer.
摘要翻译：一种半导体器件，包括：具有主表面的半导体基板，其具有一栅极和第一和第二扩散区和其上主表面形成的MOS晶体管。半导体器件还包括SOG层的层叠结构，其中层叠结构由基底层和形成在基底层上的表面层组成。层叠结构形成在MOS晶体管的上方，表面层比基层更致密。

8. 发明授权

US07105464B2 Semiconductor device and method of fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07105464B2
公开(公告)日：2006-09-12
申请号：US10862331
申请日：2004-06-08
申请人： Kazuhiko Asakawa , Wataru Shimizu
发明人： Kazuhiko Asakawa , Wataru Shimizu
IPC分类号： H01L21/4763 , H01L21/469 , H01L21/324
CPC分类号： H01L21/76897 , H01L21/76801 , H01L21/76802 , H01L21/76825 , H01L23/3192 , H01L23/5258 , H01L27/10808 , H01L27/10873 , H01L2924/0002 , H01L2924/19041 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate which has a major surface and a MOS transistor which has a gate and first and second diffusion regions and which is formed on the major surface. The semiconductor device also includes a laminated structure of a SOG layer, wherein the laminated structure is composed of a base layer and a surface layer formed on the base layer and is formed over the MOS transistor and wherein the surface layer is denser than the base layer.
摘要翻译：半导体器件包括具有主表面的半导体衬底和具有栅极和第一和第二扩散区域并且形成在主表面上的MOS晶体管。半导体器件还包括SOG层的层叠结构，其中层叠结构由基底层和形成在基底层上的表面层组成并形成在MOS晶体管上，并且其中表面层比基底层更致密。

9. 发明授权

US06782512B2 Fabrication method for a semiconductor device with dummy patterns 失效
标题翻译：具有虚拟图案的半导体器件的制造方法
公开(公告)号：US06782512B2
公开(公告)日：2004-08-24
申请号：US10124391
申请日：2002-04-18
申请人： Kazuhiko Asakawa
发明人： Kazuhiko Asakawa
IPC分类号： G06F1750
CPC分类号： H01L21/76838 , H01L21/31053 , H01L21/76819 , Y10S438/926
摘要： A semiconductor device is fabricated by a method that includes forming a conductive pattern on a semiconductor substrate, covering the conductive pattern with a dielectric layer, and planarizing the dielectric layer by chemical-mechanical polishing. To avoid global height differences, a dummy pattern is added to the conductive pattern if a predetermined condition is satisfied. The condition is based on the calculated density of the conductive pattern in a region including the region in which the dummy pattern is to be added. The calculated density may be adjusted according to the type of equipment used to deposit the dielectric layer, and the dummy pattern dimensions may be adjusted according to the calculated density. Such calculations avoid the need for human judgment and lead to more uniform planarization.
摘要翻译：通过包括在半导体衬底上形成导电图案的方法制造半导体器件，用电介质层覆盖导电图案，并通过化学机械抛光来平坦化介电层。为了避免全局高度差异，如果满足预定条件，则将虚拟图案添加到导电图案。该条件基于在包括要添加虚拟图案的区域的区域中的导电图案的计算密度。可以根据用于沉积介电层的设备的类型来调节计算的密度，并且可以根据计算的密度来调整虚拟图案尺寸。这样的计算避免了对人的判断的需要，并导致更均匀的平面化。

10. 发明申请

US20110089569A1 Multilayer wiring, method for placing dummy wiring in multilayer wiring, semiconductor device, and semiconductor device manufacturing method 审中-公开
标题翻译：多层布线，将布线布置在多层布线中的方法，半导体器件和半导体器件制造方法
公开(公告)号：US20110089569A1
公开(公告)日：2011-04-21
申请号：US12801551
申请日：2010-06-14
申请人： Kazuhiko Asakawa
发明人： Kazuhiko Asakawa
IPC分类号： H01L23/52 , H01L21/768
CPC分类号： H01L23/522 , G06F17/5077 , G06F2217/12 , H01L21/76819 , H01L2924/0002 , Y02P90/265 , H01L2924/00
摘要： A multilayer wiring in which plural metal wirings and plural interlayer insulating films are layered, each interlayer insulating film being planarized each time formed, is divided into plural regions. The percentage of an area occupied by each of the metal wirings within each region is obtained for each of the metal wirings. An integral percentage is obtained per region by integrating, the percentages. The integral percentages are used to calculate the relative positional relationship of upper surfaces of the interlayer insulating films of plural regions, from the relative values of the integral percentages obtained beforehand and relative positions of the upper surfaces. In regions where the upper surface is of a height lower than a predetermined value, a dummy wiring is disposed, and in regions where the upper surface is of a height equal to or greater than the predetermined value, a dummy wiring is not disposed.
摘要翻译：将多层金属布线和多层层间绝缘膜分层的多层布线，每层形成的层间绝缘膜平坦化，分成多个区域。对于每个金属布线，获得每个区域内的每个金属布线占据的面积的百分比。通过积分百分比获得每个区域的积分百分比。根据预先获得的积分百分数的相对值和上表面的相对位置，使用积分百分比来计算多个区域的层间绝缘膜的上表面的相对位置关系。在上表面的高度低于预定值的区域中，设置虚设布线，并且在上表面的高度等于或大于预定值的区域中，不布置虚拟布线。

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