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    • 2. 发明授权
    • Moving picture conversion apparatus
    • 运动图像转换装置
    • US07933335B2
    • 2011-04-26
    • US11287052
    • 2005-11-25
    • Hiroshi IkedaMasaki Maeda
    • Hiroshi IkedaMasaki Maeda
    • H04N11/02H04N11/04
    • H04N19/577H04N19/105H04N19/159H04N19/172H04N19/40H04N19/51H04N19/52H04N19/61
    • A moving picture conversion apparatus converts first moving image data encoded in accordance with a first motion compensated prediction method into second moving picture data that has a same format as data encoded in accordance with a second motion compensated prediction method. The moving picture conversion apparatus determines whether a relationship between a block in the second motion compensation method and an image used as a reference image with respect to the block confirms with a condition. When the relationship is determined to confirm with the condition, the moving picture conversion apparatus performs encoding using a motion vector or vectors of the first moving image data corresponding to the block.
    • 运动图像转换装置将根据第一运动补偿预测方法编码的第一运动图像数据转换成与根据第二运动补偿预测方法编码的数据具有相同格式的第二运动图像数据。 运动图像转换装置确定第二运动补偿方法中的块与用作参考图像的图像之间的关系是否符合条件。 当确定该关系以确认条件时,运动图像转换装置使用运动矢量或对应于该块的第一运动图像数据的向量来执行编码。
    • 4. 发明授权
    • Array type operation device
    • 阵列式操作装置
    • US07606996B2
    • 2009-10-20
    • US11572701
    • 2005-08-02
    • Hiroyuki MorishitaTakeshi TanakaMasaki MaedaYorihiko Wakayama
    • Hiroyuki MorishitaTakeshi TanakaMasaki MaedaYorihiko Wakayama
    • G06F15/80
    • G06F15/8007G06F1/3203G06F9/3842G06F9/3885H04N19/43H04N19/61
    • An array calculation device that includes a processor array composed of a plurality of processor elements having been assigned with orders, acquires an instruction in each cycle, generates, in each cycle, operation control information for controlling an operation of a processor element of a first order, and then generates an instruction to the processor element of the first order in accordance with the operation control information and the acquired instruction, and also generates, in each cycle, operation control information for controlling an operation of each processor element of a next order and onwards, in accordance with operation control information generated for controlling an operation of a processor element of an immediately preceding order, and then generates an instruction to each processor element of the next order and onwards, in accordance with the operation control information generated and the acquired instruction.
    • 一种阵列计算装置,包括由已经被分配了多个处理器元件的处理器阵列组成的处理器阵列,获取每个周期中的指令,在每个周期中生成用于控制一阶处理器元件的操作的操作控制信息 ,然后根据操作控制信息和获取的指令向第一级处理器单元生成指令,并且在每个周期中还生成用于控制下一个订单的每个处理器元件的操作的操作控制信息,以及 根据生成的用于控制紧接在前的顺序的处理器元件的操作的操作控制信息,然后根据产生的和所获取的操作控制信息产生对下一个订单的每个处理器元件的指令 指令。
    • 9. 发明授权
    • Reconfigurable computing circuit
    • 可重构计算电路
    • US07996657B2
    • 2011-08-09
    • US12105551
    • 2008-04-18
    • Masaki MaedaTakahiro Ichinomiya
    • Masaki MaedaTakahiro Ichinomiya
    • G06F7/38G06F9/00
    • G06F15/7867
    • A reconfigurable computing circuit for reducing the amount of dummy data to be stored in data registers, which is required when the wiring is shared by the configuration information bus and scan chain. When data is to be stored in data registers and configuration registers constituting the scan chain in reconfig computing block 2010, reg setting data selecting unit 3400 selects either a value stored in reg setting data storage unit 3000 or an initial value output from data reg data generating unit 4000, based on the information stored in reg type managing unit 1100 that indicates the types of registers and the connection order of the registers in the scan chain, and outputs the selected value in sequence to the scan chain under control of scan/reconfig control unit 1000. Each register in the scan chain then shifts data stored therein to the next register in the scan chain in sequence.
    • 一种可重配置计算电路,用于减少存储在数据寄存器中的伪数据的数量,这是当配置信息总线和扫描链共享布线时所需要的。 当数据被存储在重构计算块2010中构成扫描链的数据寄存器和配置寄存器中时,寄存器设置数据选择单元3400选择存储在寄存器设置数据存储单元3000中的值或从数据寄存器数据生成产生的初始值 单元4000,基于存储在寄存器类型管理单元1100中的信息,其指示扫描链中的寄存器的类型和寄存器的连接顺序,并且在扫描/重新配置控制的控制下将所选择的值依次输出到扫描链 单元1000.扫描链中的每个寄存器然后将存储在其中的数据顺序地移动到扫描链中的下一个寄存器。
    • 10. 发明申请
    • MULTI THREAD PROCESSOR HAVING DYNAMIC RECONFIGURATION LOGIC CIRCUIT
    • 具有动态重构逻辑电路的多线程处理器
    • US20090307470A1
    • 2009-12-10
    • US12093884
    • 2006-11-21
    • Masaki MaedaHideshi NishidaYorihiko Wakayama
    • Masaki MaedaHideshi NishidaYorihiko Wakayama
    • G06F9/318
    • G06F15/7867
    • A processor according to the present invention cyclically executes a plurality of threads, for each time period allocated thereto. The processor stores, for each thread, configuration information of operation cells. Each of the threads causes the execution of a different predetermined number of operation cells in series, and successively reconfigures an operation cell that has completed a last operation thereof in the time period allocated to a current thread, based on a stored piece of configuration information of the operation cell that corresponds to a next thread, and causes concurrent execution of an operation cell having a configuration for the current thread and (ii) an operation cell having a configuration for the next thread.
    • 根据本发明的处理器在分配给它的每个时间段周期性地执行多个线程。 处理器为每个线程存储操作单元的配置信息。 每个线程使得执行不同的预定数量的操作单元串联,并且在分配给当前线程的时间段内,基于存储的一条配置信息,连续地重新配置已经完成其最后操作的操作单元 对应于下一个线程的操作单元,并且使具有当前线程的配置的操作单元并行执行,以及(ii)具有下一个线程的配置的操作单元。