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1. 发明授权

US08154072B2 Nonvolatile semiconductor memory apparatus 有权
标题翻译：非易失性半导体存储装置
公开(公告)号：US08154072B2
公开(公告)日：2012-04-10
申请号：US12403493
申请日：2009-03-13
申请人： Masahiro Koike , Yuichiro Mitani , Tatsuo Shimizu , Naoki Yasuda , Yasushi Nakasaki , Akira Nishiyama
发明人： Masahiro Koike , Yuichiro Mitani , Tatsuo Shimizu , Naoki Yasuda , Yasushi Nakasaki , Akira Nishiyama
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L29/513
摘要： A nonvolatile semiconductor memory apparatus includes: a source and drain regions formed at a distance from each other in a semiconductor layer; a first insulating film formed on the semiconductor layer located between the source region and the drain region, the first insulating film including a first insulating layer and a second insulating layer formed on the first insulating layer and having a higher dielectric constant than the first insulating layer, the second insulating layer having a first site performing hole trapping and releasing, the first site being formed by adding an element different from a base material to the second insulating film, the first site being located at a lower level than a Fermi level of a material forming the semiconductor layer; a charge storage film formed on the first insulating film; a second insulating film formed on the charge storage film; and a control gate electrode formed on the second insulating film.
摘要翻译：一种非易失性半导体存储器件，包括：在半导体层中形成为彼此间隔一定距离的源区和漏区; 形成在位于源极区域和漏极区域之间的半导体层上的第一绝缘膜，所述第一绝缘膜包括形成在所述第一绝缘层上并具有比所述第一绝缘层高的介电常数的第一绝缘层和第二绝缘层所述第二绝缘层具有进行孔捕获和释放的第一部位，所述第一部位通过将不同于基材的元素添加到所述第二绝缘膜而形成，所述第一部位位于比所述第二绝缘膜的费米能级更低的水平形成半导体层的材料; 形成在所述第一绝缘膜上的电荷存储膜; 形成在电荷存储膜上的第二绝缘膜; 以及形成在所述第二绝缘膜上的控制栅电极。

2. 发明申请

US20100052035A1 NONVOLATILE SEMICONDUCTOR MEMORY APPARATUS 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20100052035A1
公开(公告)日：2010-03-04
申请号：US12403493
申请日：2009-03-13
申请人： Masahiro KOIKE , Yuichiro Mitani , Tatsuo Shimizu , Naoki Yasuda , Yasushi Nakasaki , Akira Nishiyama
发明人： Masahiro KOIKE , Yuichiro Mitani , Tatsuo Shimizu , Naoki Yasuda , Yasushi Nakasaki , Akira Nishiyama
IPC分类号： H01L29/788 , H01L29/792
CPC分类号： H01L29/7881 , H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L29/513
摘要： A nonvolatile semiconductor memory apparatus includes: a source and drain regions formed at a distance from each other in a semiconductor layer; a first insulating film formed on the semiconductor layer located between the source region and the drain region, the first insulating film including a first insulating layer and a second insulating layer formed on the first insulating layer and having a higher dielectric constant than the first insulating layer, the second insulating layer having a first site performing hole trapping and releasing, the first site being formed by adding an element different from a base material to the second insulating film, the first site being located at a lower level than a Fermi level of a material forming the semiconductor layer; a charge storage film formed on the first insulating film; a second insulating film formed on the charge storage film; and a control gate electrode formed on the second insulating film.
摘要翻译：一种非易失性半导体存储器件，包括：在半导体层中形成为彼此间隔一定距离的源区和漏区; 形成在位于源极区域和漏极区域之间的半导体层上的第一绝缘膜，所述第一绝缘膜包括形成在所述第一绝缘层上并具有比所述第一绝缘层高的介电常数的第一绝缘层和第二绝缘层所述第二绝缘层具有进行孔捕获和释放的第一部位，所述第一部位通过将不同于基材的元素添加到所述第二绝缘膜而形成，所述第一部位位于比所述第二绝缘膜的费米能级更低的水平形成半导体层的材料; 形成在所述第一绝缘膜上的电荷存储膜; 形成在电荷存储膜上的第二绝缘膜; 以及形成在所述第二绝缘膜上的控制栅电极。

3. 发明申请

US20100244157A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100244157A1
公开(公告)日：2010-09-30
申请号：US12710851
申请日：2010-02-23
申请人： Izumi HIRANO , Yuichiro Mitani , Tatsuo Shimizu , Yasushi Nakasaki , Akiko Masada , Shigeto Fukatsu , Masahiro Koike
发明人： Izumi HIRANO , Yuichiro Mitani , Tatsuo Shimizu , Yasushi Nakasaki , Akiko Masada , Shigeto Fukatsu , Masahiro Koike
IPC分类号： H01L29/78
CPC分类号： H01L29/7833 , H01L21/28079 , H01L29/4958 , H01L29/513 , H01L29/518 , H01L29/665 , H01L29/6659
摘要： A semiconductor device includes a MISFET comprising: a semiconductor layer including a semiconductor region formed therein; a gate insulating film formed above the semiconductor region, and including a metal oxide layer containing a metal and oxygen, the metal contained in the metal oxide layer being at least one selected from Hf and Zr, the metal oxide layer further including at least one element selected from the group consisting of Ru, Cr, Os, V, Tc, and Nb, the metal oxide layer having sites that capture or release charges formed by inclusion of the element, density of the element in the metal oxide layer being in the range of 1×1015 cm−3 to 2.96×1020 cm−3, the sites being distributed to have a peak closer to the semiconductor region than to a center of the metal oxide layer; and a gate electrode formed on the gate insulating film.
摘要翻译：半导体器件包括：MISFET，包括：半导体层，包括形成在其中的半导体区域; 形成在所述半导体区域上方的栅极绝缘膜，并且包括含有金属和氧的金属氧化物层，所述金属氧化物层中所含的金属为选自Hf和Zr中的至少一种，所述金属氧化物层还包含至少一种元素选自Ru，Cr，Os，V，Tc和Nb的金属氧化物层，金属氧化物层具有捕获或释放由元素包含形成的电荷的部位，金属氧化物层中的元素的密度在该范围内 1×1015cm-3至2.96×1020cm-3，这些位置被分配成具有比金属氧化物层的中心更靠近半导体区域的峰; 以及形成在栅极绝缘膜上的栅电极。

4. 发明授权

US08476718B2 Semiconductor device including a gate insulating film having a metal oxide layer having trap levels 有权
标题翻译：半导体器件包括具有陷阱电平的金属氧化物层的栅极绝缘膜
公开(公告)号：US08476718B2
公开(公告)日：2013-07-02
申请号：US12710851
申请日：2010-02-23
申请人： Izumi Hirano , Yuichiro Mitani , Tatsuo Shimizu , Yasushi Nakasaki , Akiko Masada , Shigeto Fukatsu , Masahiro Koike
发明人： Izumi Hirano , Yuichiro Mitani , Tatsuo Shimizu , Yasushi Nakasaki , Akiko Masada , Shigeto Fukatsu , Masahiro Koike
IPC分类号： H01L21/02
CPC分类号： H01L29/7833 , H01L21/28079 , H01L29/4958 , H01L29/513 , H01L29/518 , H01L29/665 , H01L29/6659
摘要： A semiconductor device includes a MISFET comprising: a semiconductor layer including a semiconductor region formed therein; a gate insulating film formed above the semiconductor region, and including a metal oxide layer containing a metal and oxygen, the metal contained in the metal oxide layer being at least one selected from Hf and Zr, the metal oxide layer further including at least one element selected from the group consisting of Ru, Cr, Os, V, Tc, and Nb, the metal oxide layer having sites that capture or release charges formed by inclusion of the element, density of the element in the metal oxide layer being in the range of 1×1015 cm−3 to 2.96×1020 cm−3, the sites being distributed to have a peak closer to the semiconductor region than to a center of the metal oxide layer; and a gate electrode formed on the gate insulating film.
摘要翻译：半导体器件包括：MISFET，包括：半导体层，包括形成在其中的半导体区域; 形成在所述半导体区域上方的栅极绝缘膜，并且包括含有金属和氧的金属氧化物层，所述金属氧化物层中所含的金属为选自Hf和Zr中的至少一种，所述金属氧化物层还包含至少一种元素选自Ru，Cr，Os，V，Tc和Nb的金属氧化物层，金属氧化物层具有捕获或释放由元素包含形成的电荷的部位，金属氧化物层中的元素的密度在该范围内 1×1015cm-3至2.96×1020cm-3，这些位置被分配成具有比金属氧化物层的中心更靠近半导体区域的峰; 以及形成在栅极绝缘膜上的栅电极。

5. 发明授权

US08592892B2 Nonvolatile semiconductor memory device and method for manufacturing the same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08592892B2
公开(公告)日：2013-11-26
申请号：US11898603
申请日：2007-09-13
申请人： Yuichiro Mitani , Masahiro Koike , Yasushi Nakasaki , Daisuke Matsushita
发明人： Yuichiro Mitani , Masahiro Koike , Yasushi Nakasaki , Daisuke Matsushita
IPC分类号： H01L29/66
CPC分类号： H01L29/7881 , H01L21/28273 , H01L21/28282 , H01L29/42324 , H01L29/513 , H01L29/792
摘要： A nonvolatile semiconductor memory device includes: a memory element, the memory element including: a semiconductor substrate; a first insulating film formed on a region in the semiconductor substrate located between a source region and a drain region, and having a stack structure formed with a first insulating layer, a second insulating layer, and a third insulating layer in this order, the first insulating layer including an electron trapping site, the second insulating layer not including the electron trapping site, and the third insulating layer including the electron trapping site, and the electron trapping site being located in a position lower than conduction band minimum of the first through third insulating layers while being located in a position higher than conduction band minimum of a material forming the semiconductor substrate; a charge storage film formed on the first insulating film; a second insulating film formed on the charge storage film; and a control gate electrode formed on the second insulating film.
摘要翻译：非易失性半导体存储器件包括：存储元件，所述存储元件包括：半导体衬底; 第一绝缘膜，形成在位于源区和漏区之间的半导体衬底的区域上，并且具有依次形成有第一绝缘层，第二绝缘层和第三绝缘层的堆叠结构，第一绝缘膜包含电子俘获位置的绝缘层，不包含电子俘获位置的第二绝缘层和包含电子捕获位点的第三绝缘层，并且电子捕获位点位于低于第一至第三区域的导带最小值的位置绝缘层位于高于形成半导体衬底的材料的导带最小值的位置; 形成在所述第一绝缘膜上的电荷存储膜; 形成在电荷存储膜上的第二绝缘膜; 以及形成在所述第二绝缘膜上的控制栅电极。

6. 发明申请

US20080135922A1 Nonvolatile semiconductor memory device and method for manufacturing the same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20080135922A1
公开(公告)日：2008-06-12
申请号：US11898603
申请日：2007-09-13
申请人： Yuichiro Mitani , Masahiro Koike , Yasushi Nakasaki , Daisuke Matsushita
发明人： Yuichiro Mitani , Masahiro Koike , Yasushi Nakasaki , Daisuke Matsushita
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/7881 , H01L21/28273 , H01L21/28282 , H01L29/42324 , H01L29/513 , H01L29/792
摘要： A nonvolatile semiconductor memory device includes: a memory element, the memory element including: a semiconductor substrate; a first insulating film formed on a region in the semiconductor substrate located between a source region and a drain region, and having a stack structure formed with a first insulating layer, a second insulating layer, and a third insulating layer in this order, the first insulating layer including an electron trapping site, the second insulating layer not including the electron trapping site, and the third insulating layer including the electron trapping site, and the electron trapping site being located in a position lower than conduction band minimum of the first through third insulating layers while being located in a position higher than conduction band minimum of a material forming the semiconductor substrate; a charge storage film formed on the first insulating film; a second insulating film formed on the charge storage film; and a control gate electrode formed on the second insulating film.
摘要翻译：非易失性半导体存储器件包括：存储元件，所述存储元件包括：半导体衬底; 第一绝缘膜，形成在位于源区和漏区之间的半导体衬底的区域上，并且具有依次形成有第一绝缘层，第二绝缘层和第三绝缘层的堆叠结构，第一绝缘膜包含电子俘获位置的绝缘层，不包含电子俘获位置的第二绝缘层和包含电子捕获位点的第三绝缘层，并且电子捕获位点位于低于第一至第三区域的导带最小值的位置绝缘层位于高于形成半导体衬底的材料的导带最小值的位置; 形成在所述第一绝缘膜上的电荷存储膜; 形成在电荷存储膜上的第二绝缘膜; 以及形成在所述第二绝缘膜上的控制栅电极。

7. 发明授权

US08557717B2 Method for manufacturing a semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US08557717B2
公开(公告)日：2013-10-15
申请号：US12801912
申请日：2010-07-01
申请人： Daisuke Matsushita , Koichi Muraoka , Koichi Kato , Yasushi Nakasaki , Yuichiro Mitani
发明人： Daisuke Matsushita , Koichi Muraoka , Koichi Kato , Yasushi Nakasaki , Yuichiro Mitani
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L27/11568 , C23C8/02 , C23C8/24 , C23C8/80 , H01L21/2652 , H01L21/28202 , H01L21/28238 , H01L21/28273 , H01L21/3144 , H01L21/3145 , H01L21/3185 , H01L27/115 , H01L27/11521 , H01L29/105 , H01L29/513
摘要： It is made possible to restrain generation of defects at the time of insulating film formation. A method for manufacturing a semiconductor device, includes: placing a semiconductor substrate into an atmosphere, thereby forming a nitride film on a surface of the semiconductor substrate, the atmosphere containing a first nitriding gas nitriding the surface of the semiconductor substrate and a first diluent gas not actually reacting with the semiconductor substrate, the ratio of the sum of the partial pressure of the first diluent gas and the partial pressure of the first nitriding gas to the partial pressure of the first nitriding gas being 5 or higher, and the total pressure of the atmosphere being 40 Torr or lower.
摘要翻译：可以抑制成膜时的缺陷的产生。一种制造半导体器件的方法，包括：将半导体衬底放置在大气中，从而在所述半导体衬底的表面上形成氮化物膜，所述气氛包含氮化所述半导体衬底的表面的第一氮化气体和第一稀释气体实际上不与半导体衬底反应，第一稀释气体的分压和第一氮化气体的分压与第一氮化气体的分压之和的比率为5以上，气氛为40乇或更低。

8. 发明授权

US07772129B2 Method for manufacturing a semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US07772129B2
公开(公告)日：2010-08-10
申请号：US11547691
申请日：2006-08-28
申请人： Daisuke Matsushita , Koichi Muraoka , Koichi Kato , Yasushi Nakasaki , Yuichiro Mitani
发明人： Daisuke Matsushita , Koichi Muraoka , Koichi Kato , Yasushi Nakasaki , Yuichiro Mitani
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L27/11568 , C23C8/02 , C23C8/24 , C23C8/80 , H01L21/2652 , H01L21/28202 , H01L21/28238 , H01L21/28273 , H01L21/3144 , H01L21/3145 , H01L21/3185 , H01L27/115 , H01L27/11521 , H01L29/105 , H01L29/513
摘要： It is made possible to restrain generation of defects at the time of insulating film formation. A method for manufacturing a semiconductor device, includes: placing a semiconductor substrate into an atmosphere, thereby forming a nitride film on a surface of the semiconductor substrate, the atmosphere containing a first nitriding gas nitriding the surface of the semiconductor substrate and a first diluent gas not actually reacting with the semiconductor substrate, the ratio of the sum of the partial pressure of the first diluent gas and the partial pressure of the first nitriding gas to the partial pressure of the first nitriding gas being 5 or higher, and the total pressure of the atmosphere being 40 Torr or lower.
摘要翻译：可以抑制成膜时的缺陷的产生。一种制造半导体器件的方法，包括：将半导体衬底放置在大气中，从而在所述半导体衬底的表面上形成氮化物膜，所述气氛包含氮化所述半导体衬底的表面的第一氮化气体和第一稀释气体实际上不与半导体衬底反应，第一稀释气体的分压和第一氮化气体的分压与第一氮化气体的分压之和的比率为5以上，气氛为40乇或更低。

9. 发明申请

US20080173927A1 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20080173927A1
公开(公告)日：2008-07-24
申请号：US11896860
申请日：2007-09-06
申请人： Kiwamu Sakuma , Daisuke Matsushita , Koichi Kato , Yasushi Nakasaki , Izumi Hirano , Kouichi Muraoka , Yuichiro Mitani , Shigeto Fukatsu , Toshihide Ito
发明人： Kiwamu Sakuma , Daisuke Matsushita , Koichi Kato , Yasushi Nakasaki , Izumi Hirano , Kouichi Muraoka , Yuichiro Mitani , Shigeto Fukatsu , Toshihide Ito
IPC分类号： H01L29/788 , H01L21/336 , H01L29/792
CPC分类号： H01L21/28273
摘要： A semiconductor device includes: a semiconductor substrate; a source region and a drain region formed at a distance from each other in the semiconductor substrate; a first insulating film formed on a portion of the semiconductor substrate, the portion being located between the source region and the drain region; a charge storage film formed on the first insulating film; a second insulating film formed above the charge storage film and made of a high-permittivity material; a control gate electrode formed above the second insulating film; and a silicon nitride layer including nitrogen atoms having three-coordinate nitrogen bonds, at least one of second-nearest neighbor atoms of the nitrogen atoms being a nitrogen atom. At least one of the charge storage film and the control gate electrode contains silicon, the silicon nitride layer is located between the second insulating film and the at least one of the charge storage film and the control gate electrode.
摘要翻译：半导体器件包括：半导体衬底; 在半导体衬底中形成为彼此间隔一定距离的源极区域和漏极区域; 形成在半导体衬底的一部分上的第一绝缘膜，该部分位于源区和漏区之间; 形成在所述第一绝缘膜上的电荷存储膜; 形成在电荷存储膜上方并由高介电常数材料制成的第二绝缘膜; 形成在所述第二绝缘膜上方的控制栅电极; 和包含具有三配位氮键的氮原子的氮化硅层，氮原子的第二最近邻原子中的至少一个为氮原子。电荷存储膜和控制栅电极中的至少一个包含硅，氮化硅层位于第二绝缘膜和电荷存储膜和控制栅电极中的至少一个之间。

10. 发明申请

US20110003481A1 Method for manufacturing a semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US20110003481A1
公开(公告)日：2011-01-06
申请号：US12801912
申请日：2010-07-01
申请人： Daisuke Matsushita , Koichi Muraoka , Koichi Kato , Yasushi Nakasaki , Yuichiro Mitani
发明人： Daisuke Matsushita , Koichi Muraoka , Koichi Kato , Yasushi Nakasaki , Yuichiro Mitani
IPC分类号： H01L21/314
CPC分类号： H01L27/11568 , C23C8/02 , C23C8/24 , C23C8/80 , H01L21/2652 , H01L21/28202 , H01L21/28238 , H01L21/28273 , H01L21/3144 , H01L21/3145 , H01L21/3185 , H01L27/115 , H01L27/11521 , H01L29/105 , H01L29/513
摘要： It is made possible to restrain generation of defects at the time of insulating film formation. A method for manufacturing a semiconductor device, includes: placing a semiconductor substrate into an atmosphere, thereby forming a nitride film on a surface of the semiconductor substrate, the atmosphere containing a first nitriding gas nitriding the surface of the semiconductor substrate and a first diluent gas not actually reacting with the semiconductor substrate, the ratio of the sum of the partial pressure of the first diluent gas and the partial pressure of the first nitriding gas to the partial pressure of the first nitriding gas being 5 or higher, and the total pressure of the atmosphere being 40 Torr or lower.
摘要翻译：可以抑制成膜时的缺陷的产生。一种制造半导体器件的方法，包括：将半导体衬底放置在大气中，从而在所述半导体衬底的表面上形成氮化物膜，所述气氛包含氮化所述半导体衬底的表面的第一氮化气体和第一稀释气体实际上不与半导体衬底反应，第一稀释气体的分压和第一氮化气体的分压与第一氮化气体的分压之和的比率为5以上，气氛为40乇或更低。

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