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1. 发明申请

US20070190669A1 Method of manufacturing a magnetoelectronic device 有权
标题翻译：制造磁电子器件的方法
公开(公告)号：US20070190669A1
公开(公告)日：2007-08-16
申请号：US11351610
申请日：2006-02-10
申请人： Mark Durlam , Gloria Kerszykowski , Nicholas Rizzo , Eric Salter , Loren Wise
发明人： Mark Durlam , Gloria Kerszykowski , Nicholas Rizzo , Eric Salter , Loren Wise
IPC分类号： H01L21/00
CPC分类号： H01L43/12
摘要： A method of manufacturing a magnetoelectronic device includes providing an electrically conducting material and an electrically insulating material adjacent to at least a portion of the electrically conducting material, and implanting a magnetic material into the electrically insulating material. The magnetic material increases the magnetic permeability of the electrically insulating material. The implant may be a blanket or a targeted implant.
摘要翻译：制造磁电子器件的方法包括提供导电材料和与导电材料的至少一部分相邻的电绝缘材料，以及将磁性材料注入到电绝缘材料中。磁性材料增加了电绝缘材料的磁导率。植入物可以是毯子或靶向植入物。

2. 发明申请

US20070260962A1 Methods and apparatus for a memory device with self-healing reference bits 有权
标题翻译：具有自修复参考位的存储器件的方法和装置
公开(公告)号：US20070260962A1
公开(公告)日：2007-11-08
申请号：US11416850
申请日：2006-05-02
申请人： Loren Wise , Thomas Andre , Mark Durlam , Eric Salter
发明人： Loren Wise , Thomas Andre , Mark Durlam , Eric Salter
IPC分类号： G11C29/00
CPC分类号： G11C29/52 , G06F11/1008 , G11C11/16
摘要： A memory device, such an MRAM device, includes self-healing reference bits (104) associated with a set of array bits (102). The memory performs an error detection step (e.g., using an error-correction coding (ECC) algorithm, to detect the presence of a set of errors within the data bits. One of the reference bits (104) is toggled to a different state if an error count is greater than a predetermined threshold. If the set of errors remains unchanged when subsequently read, the reference bit (104) is toggled back to its original state.
摘要翻译：诸如MRAM设备的存储器件包括与一组阵列位（102）相关联的自修复参考位（104）。存储器执行错误检测步骤（例如，使用纠错编码（ECC）算法）来检测数据位内的一组错误的存在，其中一个参考位（104）被切换到不同的状态，如果错误计数大于预定阈值，如果随后读取的错误集合保持不变，则将参考位（104）切换回其初始状态。

3. 发明申请

US20070045759A1 Passive elements in MRAM embedded integrated circuits 有权
公开(公告)号：US20070045759A1
公开(公告)日：2007-03-01
申请号：US11217146
申请日：2005-08-31
申请人： Young Chung , Robert Baird , Mark Durlam , Gregory Grynkewich , Eric Salter
发明人： Young Chung , Robert Baird , Mark Durlam , Gregory Grynkewich , Eric Salter
IPC分类号： H01L43/00
CPC分类号： H01L27/228
摘要： An integrated circuit device (300) comprises a substrate (301) and MRAM architecture (314) formed on the substrate (308). The MRAM architecture (314) includes a MRAM circuit (318) formed on the substrate (301); and a MRAM cell (316) coupled to and formed above the MRAM circuit (318). Additionally a passive device (320) is formed in conjunction with the MRAM cell (316). The passive device (320) can be one or more resistors and one or more capacitor. The concurrent fabrication of the MRAM architecture (314) and the passive device (320) facilitates an efficient and cost effective use of the physical space available over active circuit blocks of the substrate (404, 504), resulting in three-dimensional integration.

4. 发明申请

US20070002609A1 MRAM embedded smart power integrated circuits 有权
标题翻译： MRAM嵌入式智能电源集成电路
公开(公告)号：US20070002609A1
公开(公告)日：2007-01-04
申请号：US11170874
申请日：2005-06-30
申请人： Young Chung , Robert Baird , Mark Durlam , Gregory Grynkewich , Eric Salter
发明人： Young Chung , Robert Baird , Mark Durlam , Gregory Grynkewich , Eric Salter
IPC分类号： G11C11/14
CPC分类号： G11C11/1659 , H01F10/3254
摘要： An integrated circuit device includes a magnetic random access memory (“MRAM”) architecture and a smart power integrated circuit architecture formed on the same substrate using the same fabrication process technology. The fabrication process technology is a modular process having a front end process and a back end process. In the example embodiment, the smart power architecture includes a power circuit component, a digital logic component, and an analog control component formed by the front end process, and a sensor architecture formed by the back end process. The MRAM architecture includes an MRAM circuit component formed by the front end process and an MRAM cell array formed by the back end process. In one practical embodiment, the sensor architecture includes a sensor component that is formed from the same magnetic tunnel junction core material utilized by the MRAM cell array. The concurrent fabrication of the MRAM architecture and the smart power architecture facilitates an efficient and cost effective use of the physical space available over active circuit blocks of the substrate, resulting in three-dimensional integration.
摘要翻译：集成电路装置包括使用相同的制造工艺技术在同一衬底上形成的磁性随机存取存储器（“MRAM”）架构和智能电力集成电路架构。制造工艺技术是具有前端工艺和后端工艺的模块化工艺。在该示例性实施例中，智能功率架构包括由前端处理形成的电源电路部件，数字逻辑部件和模拟控制部件以及由后端处理形成的传感器架构。 MRAM架构包括由前端处理形成的MRAM电路部件和由后端处理形成的MRAM单元阵列。在一个实际实施例中，传感器架构包括由MRAM单元阵列使用的相同的磁性隧道结芯体材料形成的传感器部件。 MRAM架构和智能电源架构的并行制造有助于在衬底的有源电路块上可用的物理空间的有效和成本有效的使用，导致三维集成。

5. 发明申请

US20050047198A1 Method of writing to a multi-state magnetic random access memory cell 失效
标题翻译：写入多状态磁随机存取存储单元的方法
公开(公告)号：US20050047198A1
公开(公告)日：2005-03-03
申请号：US10647976
申请日：2003-08-25
申请人： Bradley Engel , Eric Salter , Jon Slaughter
发明人： Bradley Engel , Eric Salter , Jon Slaughter
IPC分类号： G11C11/15 , G11C11/16 , G11C11/56 , G11C11/00
CPC分类号： G11C11/16 , G11C11/5607
摘要： A method to switch a scalable magnetoresistive memory cell including the steps of providing a magnetoresistive memory device (12) having two bits (18) and (20) sandwiched between a word line (14) and a digit line (16) so that current waveforms (104) and (106) can be applied to the word and digit lines at various times to cause a magnetic field flux HW and HD to rotate the effective magnetic moment vectors (86) and (94) of the device (12) by approximately 180°. Each bit includes N ferromagnetic layers (32) and (34, 42) and (44, 60) and (62, 72 and 74) that are anti-ferromagnetically coupled. N can be adjusted to change the magnetic switching volume of the bit. One or both bits may be programmed by adjusting the current in the word and/or digit lines.
摘要翻译：一种用于切换可扩展磁阻存储单元的方法，包括以下步骤：提供具有夹在字线（14）和数字线（16）之间的两个位（18）和（20）的磁阻存储器件（12），使得电流波形（104）和（106）可以在不同时间施加到字和数字线，以使磁场通量HW和HD将装置（12）的有效磁矩矢量（86）和（94）旋转大约 180°。每个位包括反铁磁耦合的N个铁磁层（32）和（34,42）和（44,60）和（62,72和74）。可以调节N以改变位的磁开关量。可以通过调整字和/或数字线中的电流来编程一个或两个位。

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