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    • 2. 发明授权
    • Phase noise tolerant sampling
    • 相位容差采样
    • US08558728B1
    • 2013-10-15
    • US13559909
    • 2012-07-27
    • Mark Alan LemkinThor Nelson Juneau
    • Mark Alan LemkinThor Nelson Juneau
    • H03M1/50
    • H03L7/08G01R31/31709H03L7/18
    • Phase noise in a first clock signal is measured using a time to digital converter (TDC) by determining variations in the phase delay between the first clock signal and a second clock signal. The TDC can include first and second series interconnections of delay elements, first and second sets of latches, and processing circuitry coupled to the latches and configured to determine the phase delay. The TDC can include a series interconnection of delay elements, latches, and circuitry configured to selectively adjust the control signal connected to the delay elements based on the output of the latches. The phase noise measurement can be used in a sampling circuit, so as to produce a second data signal from a first data signal based on the first clock signal and the measured phase noise.
    • 通过确定第一时钟信号和第二时钟信号之间的相位延迟的变化,使用时间数字转换器(TDC)测量第一时钟信号中的相位噪声。 TDC可以包括延迟元件的第一和第二串联互连,第一和第二锁存器组以及耦合到锁存器并被配置为确定相位延迟的处理电路。 TDC可以包括延迟元件,锁存器和配置为基于锁存器的输出选择性地调整连接到延迟元件的控制信号的电路的串联互连。 可以在采样电路中使用相位噪声测量,以便基于第一时钟信号和所测量的相位噪声从第一数据信号产生第二数据信号。