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1. 发明授权

US09611033B1 System and method for maintaining system integrity in control systems having multi-lane computational differences 有权
公开(公告)号：US09611033B1
公开(公告)日：2017-04-04
申请号：US14864846
申请日：2015-09-24
申请人： Mark A. Kovalan , Mark Clifford Singer , Douglas R. Johnson
发明人： Mark A. Kovalan , Mark Clifford Singer , Douglas R. Johnson
IPC分类号： B64C19/00 , G05B19/05
CPC分类号： B64C19/00 , G05B9/03 , G05B19/042 , G05B19/05
摘要： A control system for an aircraft including first and second lanes having respective first and second processors dissimilar to one another and configured to output respective first and second computation data. At least one programmable logic device may be configured to receive the first computation data output and the second computation data output, determine a difference therebetween, and transmit a corrective computation data output to the first processor and the second processor via respective feedback loops if the difference between the first computation data output and the second computation data output exceeds a predetermined threshold value.

2. 发明授权

US09454418B1 Method for testing capability of dissimilar processors to achieve identical computations 有权
标题翻译：用于测试不同处理器的能力以实现相同计算的方法
公开(公告)号：US09454418B1
公开(公告)日：2016-09-27
申请号：US14465077
申请日：2014-08-21
申请人： Mark A. Kovalan , Mark Clifford Singer
发明人： Mark A. Kovalan , Mark Clifford Singer
IPC分类号： G06F11/07
CPC分类号： G06F11/2215
摘要： A method for testing processors includes generating, from a set of input bits, a first set of machine data bits in a first processor and a second set of machine data bits in a second processor dissimilar to the first processor, and comparing the first and second sets of machine data bits to output a first comparison result. The method also includes generating, from a third set of machine data bits, a first and second sets of machine result bits, and comparing the first and second sets of machine result bits to output a second comparison result. The method further includes generating, from a fourth set of machine data bits, a first and second sets of output bits, and comparing the first and second sets of output bits to output a third comparison result. The method also includes determining whether the first and second processors operate substantially similar to each other based on at least one of the first, second, and third comparison results.
摘要翻译：一种用于测试处理器的方法包括：从一组输入比特中生成与第一处理器不同的第二处理器中的第一处理器中的第一组机器数据位和第二组机器数据位，以及将第一和第二机组数据位组，以输出第一比较结果。该方法还包括从第三组机器数据位生成第一和第二组机器结果位，并且比较第一和第二组机器结果位以输出第二比较结果。该方法还包括从第四组机器数据位生成第一和第二组输出位，并且比较第一和第二组输出位以输出第三比较结果。该方法还包括基于第一，第二和第三比较结果中的至少一个来确定第一和第二处理器是否基本相似。

3. 发明授权

US09612985B1 Synchronization mechanisms for high-integrity computing 有权
公开(公告)号：US09612985B1
公开(公告)日：2017-04-04
申请号：US14462955
申请日：2014-08-19
申请人： Mark A. Kovalan , Mark Clifford Singer , Douglas L. Bader , Douglas Robert Johnson , John William Roltgen, III
发明人： Mark A. Kovalan , Mark Clifford Singer , Douglas L. Bader , Douglas Robert Johnson , John William Roltgen, III
IPC分类号： G06F11/00 , G06F13/372
CPC分类号： G06F13/372 , G06F13/364
摘要： A system includes a first plurality of processors, a second plurality of processors dissimilar from the first plurality of processors, a first arbitration device coupled to the first plurality of processors, and a second arbitration device coupled to the second plurality of processors. The first arbitration device and the second arbitration device is configured to receive event data, store the received event data, and to output the received event data at substantially a same time. At least one processor of the first plurality of processors and at least one processor of the second plurality of processors are configured to access the event data.

4. 发明授权

US07852235B1 High integrity computing via input synchronization systems and methods 有权
标题翻译：通过输入同步系统和方法实现高完整性计算
公开(公告)号：US07852235B1
公开(公告)日：2010-12-14
申请号：US12150402
申请日：2008-04-28
申请人： Douglas R. Johnson , James J. Corcoran , Eric J. Danielson , John W. Roltgen , Mark A. Kovalan , Corydon J. Carlson , John L. Persick , Cleveland C. Gilbert , Samir S. Hemaidan , Shawn M. Stanger
发明人： Douglas R. Johnson , James J. Corcoran , Eric J. Danielson , John W. Roltgen , Mark A. Kovalan , Corydon J. Carlson , John L. Persick , Cleveland C. Gilbert , Samir S. Hemaidan , Shawn M. Stanger
IPC分类号： G08B21/00 , G08B29/00 , G06F11/00 , G01C23/00
CPC分类号： G06F11/1641 , G06F11/1637 , G06F11/1687
摘要： A method of comparing output information from dissimilar processors includes storing a task in a first memory and storing the task in a second memory at substantially the same time as the first memory. The time of the storing being is controlled by a first arbitration logic and a second arbitration logic. The method also includes receiving the task by a first processor from the first memory and receiving the task by a second processor from the memory at substantially the same time as the first processor. The time being received is controlled by a first arbitration logic and a second arbitration logic. The second processor being dissimilar to the first processor. The method further includes computing a first output by the first processor based on the task and computing a second output by the second processor based on the task. The method still further includes, synchronizing the first and second outputs so that the first and second outputs are output at substantially the same time. The synchronizing is controlled by the first and second arbitration logic.
摘要翻译：比较来自不同处理器的输出信息的方法包括将任务存储在第一存储器中，并将该任务与第一存储器基本上同时存储在第二存储器中。存储的时间由第一仲裁逻辑和第二仲裁逻辑控制。该方法还包括由第一处理器从第一存储器接收任务，并且在与第一处理器基本相同的时间，由第二处理器从存储器接收任务。所接收的时间由第一仲裁逻辑和第二仲裁逻辑控制。第二处理器与第一处理器不相似。该方法还包括基于该任务计算第一处理器的第一输出并基于该任务计算第二处理器的第二输出。该方法还包括：使第一和第二输出同步，使得第一和第二输出基本上同时输出。同步由第一和第二仲裁逻辑控制。

5. 发明授权

US06453374B1 Data bus 失效
标题翻译：数据总线
公开(公告)号：US06453374B1
公开(公告)日：2002-09-17
申请号：US09281584
申请日：1999-03-30
申请人： Mark A. Kovalan , Bryon L. Wiscons , John L. Persick , Douglas R. Johnson , Gregory E. Dunn , Stephen I. Kotalik
发明人： Mark A. Kovalan , Bryon L. Wiscons , John L. Persick , Douglas R. Johnson , Gregory E. Dunn , Stephen I. Kotalik
IPC分类号： G06F1300
CPC分类号： G06F13/4286
摘要： A bus system including a bus user apparatus and a method for communicating via the bus system are disclosed. The bus user apparatus includes means for means for selectively coupling a transmitter to the transmission line according to a protocol of the bus system. The bus system provides bi-directional communication over a single transmission line. The transmitter of the transmitting device is coupled to the transmission line during transmission. Upon completion of transmission, the transmitting device sends a permission to transmit signal to the next transmitting device according to the protocol, and decouples its transmitter from the transmission line. The next transmitting device couples its transmitter to the transmission line and begins transmission of data. Multiple bus users, both transmitters and receivers, are accommodated by the bus system, and bi-directional communication is supported. Further, the data transmission rate may be increased by selectively coupling the transmitter of a receiving device to the transmission line to provide a termination impedance on the transmission line. Higher transmission rates may be accommodated without a termination impedance; if necessary, a termination impedance may be applied. If necessary, the output voltage of the transmitter and the sensitivity of the receiver may be adjusted to accommodate the higher transmission rates. The bus system may also accommodate larger sized words. The bus system is compatible with previously existing systems compliant with an ARINC standard while providing increased capability.
摘要翻译：公开了一种包括总线用户装置和通过总线系统进行通信的方法的总线系统。总线用户装置包括用于根据总线系统的协议选择性地将发射机耦合到传输线的装置的装置。总线系统通过单个传输线提供双向通信。发射装置的发射机在传输期间耦合到传输线路。传输完成后，发送设备根据协议向下一个发送设备发送发送信号的许可，并将其发射机与传输线路分离。下一个发送设备将其发射机耦合到传输线并开始传输数据。多个总线用户（发送器和接收器）都由总线系统容纳，并支持双向通信。此外，可以通过选择性地将接收装置的发射机耦合到传输线来提供传输线上的终端阻抗来增加数据传输速率。可以容纳更高的传输速率而没有终端阻抗; 如果需要，可以施加终止阻抗。如果需要，可以调整发射机的输出电压和接收机的灵敏度以适应较高的传输速率。总线系统还可以容纳较大尺寸的字。总线系统与先前存在的符合ARINC标准的系统兼容，同时提供增强的功能。

6. 发明授权

US06694382B1 Flexible I/O subsystem architecture and associated test capability 有权
标题翻译：灵活的I / O子系统架构和相关测试能力
公开(公告)号：US06694382B1
公开(公告)日：2004-02-17
申请号：US09643060
申请日：2000-08-21
申请人： Mark A. Kovalan , Bryon L. Wiscons , Ronald W. Aull , John L. Persick
发明人： Mark A. Kovalan , Bryon L. Wiscons , Ronald W. Aull , John L. Persick
IPC分类号： G06F300
CPC分类号： G05B19/0423 , G05B2219/21012 , G05B2219/23236
摘要： A data transfer mechanism for directing data signals from signal-producing elements to signal-receiving elements is disclosed. The data transfer mechanism includes a plurality of input ports, with each input port being connected to a signal-producing element, and a plurality of output ports, with each output port being connected to a signal-receiving element. Each data signal that enters the data transfer mechanism through one of the plurality of input ports has data identification information associated therewith. The, data transfer mechanism directs the data signal to at least one of the plurality of output ports according to the data identification information associated with the data signal.
摘要翻译：公开了一种用于将数据信号从信号产生元件引导到信号接收元件的数据传送机构。数据传送机构包括多个输入端口，每个输入端口连接到信号产生元件，以及多个输出端口，每个输出端口连接到信号接收元件。通过多个输入端口之一进入数据传送机制的每个数据信号具有与其相关联的数据识别信息。数据传输机构根据与数据信号相关联的数据识别信息将数据信号引导到多个输出端口中的至少一个。

7. 发明授权

US08306421B1 Passive optical avionics network including optical repeater 有权
标题翻译：无源光学航空电子网络，包括光中继器
公开(公告)号：US08306421B1
公开(公告)日：2012-11-06
申请号：US12220014
申请日：2008-07-21
申请人： Daniel E. Mazuk , David A. Miller , Mark A. Kovalan
发明人： Daniel E. Mazuk , David A. Miller , Mark A. Kovalan
IPC分类号： H04B10/20
CPC分类号： H04B10/272 , H04B10/0793
摘要： The present disclosure is directed to a passive optical avionics network system and method.A avionics network system may comprise: (a) a passive optical network, the passive optical network comprising an optical repeater; and (b) an avionics module operably coupled to the passive optical network.An integrated modular avionics (IMA) system may comprise: (a) a line-replaceable unit (LRU), the LRU comprising: (i) a processing unit; and (ii) an optical line terminal (OLT); (b) an optical repeater; (c) at least one optical network unit (ONU); and an avionics module operably coupled to the at least one ONU.A method for avionics network communication may comprise: (a) receiving optical avionics data signals; (b) monitoring the optical avionics data signals for compliance with a communications protocol; and (c) regulating transmission of the optical avionics data signals according to compliance with the communications protocol.
摘要翻译：本公开涉及无源光学航空电子网络系统和方法。航空电子网络系统可以包括：（a）无源光网络，所述无源光网络包括光中继器; 和（b）可操作地耦合到无源光网络的航空电子模块。集成模块化航空电子（IMA）系统可以包括：（a）线路可替换单元（LRU），所述LRU包括：（i）处理单元; 和（ii）光线路终端（OLT）; （b）光中继器; （c）至少一个光网络单元（ONU）; 以及可操作地耦合到所述至少一个ONU的航空电子模块。航空电子网络通信的方法可以包括：（a）接收光学航空电子数据信号; （b）监视光学航空电子数据信号以符合通信协议; （c）根据通信协议的规定调整光学航空电子数据信号的传输。

8. 发明授权

US08015390B1 Dissimilar processor synchronization in fly-by-wire high integrity computing platforms and displays 有权
标题翻译：基于线控的高完整性计算平台和显示器的不同处理器同步
公开(公告)号：US08015390B1
公开(公告)日：2011-09-06
申请号：US12077599
申请日：2008-03-19
申请人： James J. Corcoran , Eric J. Danielson , Samir S. Hemaidan , John W. Roltgen , James E. Sisson , Mark A. Kovalan , Mark C. Singer
发明人： James J. Corcoran , Eric J. Danielson , Samir S. Hemaidan , John W. Roltgen , James E. Sisson , Mark A. Kovalan , Mark C. Singer
IPC分类号： G06F11/00
CPC分类号： G06F11/1683 , G05D1/0077 , G06F11/1641
摘要： A flight control system includes an output device, a first processor, and a second processor. The second processor is dissimilar to the first processor. The flight control system also includes a first arbitration device coupled to the first processor and a second arbitration device coupled to the second processor. The second arbitration device is configured to coordinate transaction synchronization with the first arbitration device and the first arbitration device is configured to coordinate transaction synchronization with the second arbitration device. A comparator processor is coupled to the first arbitration device and the second arbitration device. The comparator processor is configured to compare transaction synchronized outputs of the first and second processors and the comparator processor effectuates a command to the output device if the comparison is valid.
摘要翻译：飞行控制系统包括输出设备，第一处理器和第二处理器。第二个处理器与第一个处理器不同。飞行控制系统还包括耦合到第一处理器的第一仲裁设备和耦合到第二处理器的第二仲裁设备。第二仲裁设备被配置为与第一仲裁设备协调事务同步，并且第一仲裁设备被配置为与第二仲裁设备协调事务同步。比较器处理器耦合到第一仲裁设备和第二仲裁设备。比较器处理器被配置为比较第一和第二处理器的事务同步输出和比较器处理器，如果比较有效，则向输出设备执行命令。

9. 发明授权

US4620277A Multimaster CPU system with early memory addressing 失效
标题翻译：具有早期内存寻址功能的多主机CPU系统
公开(公告)号：US4620277A
公开(公告)日：1986-10-28
申请号：US470695
申请日：1983-02-28
申请人： Jimmie L. Fisher , Mark A. Kovalan , Bryon L. Wiscons
发明人： Jimmie L. Fisher , Mark A. Kovalan , Bryon L. Wiscons
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F12/0215
摘要： A circuit and technique of operation thereof are disclosed for a multimaster CPU system wherein a memory may be accessed during program operation in an average time less than that of the memory access time specification. This technique has particular usefulness in programs contained in relatively slow read-only-memory wherein a significant portion of the addresses related to memory are sequential. In optimum utilization, each master CPU has a dedicated PROM card which can only be enabled by the specified CPU. This configuration prevents additional master CPU's from interfering with the time saving benefits of early memory addressing.
摘要翻译：公开了一种用于多主机CPU系统的电路及其操作技术，其中可以在平均时间小于存储器访问时间规范的存储器的程序操作期间访问存储器。该技术对于包含在相对较慢的只读存储器中的程序具有特殊的用途，其中与存储器相关的地址的很大一部分是顺序的。在最佳利用率方面，每个主CPU都有专用的PROM卡，只能由指定的CPU启用。此配置可防止额外的主CPU干扰早期内存寻址的时间节省优势。

10. 发明授权

US08078055B1 Passive optical avionics network 有权
标题翻译：被动光电航空网络
公开(公告)号：US08078055B1
公开(公告)日：2011-12-13
申请号：US12151249
申请日：2008-05-05
申请人： Daniel E. Mazuk , Peter J. Morgan , David A. Miller , Nicholas H. Bloom , Mark A. Kovalan
发明人： Daniel E. Mazuk , Peter J. Morgan , David A. Miller , Nicholas H. Bloom , Mark A. Kovalan
IPC分类号： H04B10/20
CPC分类号： H04B10/272
摘要： The present disclosure is directed to a passive optical avionics network system and method.A passive avionics network may comprise: (a) an optical line terminal (OLT); (b) at least one optical network unit (ONU); (c) a fiber optic bus operably coupling the OLT and the ONU; and (d) an avionics module operably coupled to the ONU.An integrated modular avionics (IMA) system may comprise: (a) a line-replaceable unit (LRU), the LRU comprising: (i) a processing unit; and (ii) an optical line terminal (OLT); (b) at least one optical network unit (ONU); (c) a fiber optic bus operably coupling the LRU and the ONU; and (d) an avionics module operably coupled to the ONU.A method for avionics network communication may comprise: (a) providing avionics data; (b) transmitting the avionics data via a fiber optic network; (c) receiving the avionics data; and (d) controlling functionality of an avionics module according to the avionics data.
摘要翻译：本公开涉及无源光学航空电子网络系统和方法。被动航空电子网络可以包括：（a）光线路终端（OLT）; （b）至少一个光网络单元（ONU）; （c）可操作地耦合OLT和ONU的光纤总线; 和（d）可操作地耦合到所述ONU的航空电子模块。集成模块化航空电子（IMA）系统可以包括：（a）线路可替换单元（LRU），所述LRU包括：（i）处理单元; 和（ii）光线路终端（OLT）; （b）至少一个光网络单元（ONU）; （c）可操作地耦合LRU和ONU的光纤总线; 和（d）可操作地耦合到所述ONU的航空电子模块。航空电子网络通信的方法可以包括：（a）提供航空电子数据; （b）通过光纤网络发送航空电子数据; （c）接收航空电子数据; 以及（d）根据航空电子数据来控制航空电子模块的功能。

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