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1. 发明授权

US5254883A Electrical current source circuitry for a bus 失效
标题翻译：总线电流源电路
公开(公告)号：US5254883A
公开(公告)日：1993-10-19
申请号：US872919
申请日：1992-04-22
申请人： Mark A. Horowitz , James A. Gasbarro , Wingyu Leung
发明人： Mark A. Horowitz , James A. Gasbarro , Wingyu Leung
IPC分类号： G06F3/00 , G05F1/613 , G11C11/401 , H03K19/0175 , H03K19/0185 , H04L25/02 , H03K19/003
CPC分类号： H04L25/0282 , H03K19/018585 , H04L25/0298
摘要： Electrical current source circuitry for a bus is described. The circuitry includes transistor circuitry coupled between the bus and ground for controlling bus current, control circuitry coupled to the transistor circuitry, and a controller coupled to the control circuitry for controlling the transistor circuitry. The controller comprises a variable level circuit comprising setting circuitry for setting a desired current for the bus and transistor reference circuitry coupled to the setting circuitry. The variable level circuit provides a first voltage. Voltage reference circuitry provides a reference voltage. Comparison circuitry is coupled to the voltage reference circuitry and to the variable level circuit for comparing the first voltage with the reference voltage. Logic circuitry is responsive to a trigger signal from the comparison circuitry. An output of the logic circuitry is coupled to the control circuitry in order to turn on the transistor circuitry in a manner dependent upon an output of the logic circuitry.
摘要翻译：描述了用于总线的电流源电路。电路包括耦合在总线和地之间的晶体管电路，用于控制总线电流，耦合到晶体管电路的控制电路以及耦合到控制电路的用于控制晶体管电路的控制器。控制器包括可变电平电路，其包括用于设置用于总线的期望电流的设置电路和耦合到该设置电路的晶体管参考电路。可变电平电路提供第一电压。电压参考电路提供参考电压。比较电路耦合到电压参考电路和可变电平电路，用于将第一电压与参考电压进行比较。逻辑电路响应来自比较电路的触发信号。逻辑电路的输出耦合到控制电路，以便以取决于逻辑电路的输出的方式接通晶体管电路。

2. 发明授权

US5432823A Method and circuitry for minimizing clock-data skew in a bus system 失效
标题翻译：用于最小化总线系统中时钟数据偏移的方法和电路
公开(公告)号：US5432823A
公开(公告)日：1995-07-11
申请号：US178601
申请日：1994-01-07
申请人： James A. Gasbarro , Mark A. Horowitz , Richard M. Barth , Winston K. M. Lee , Wingyu Leung , Paul M. Farmwald
发明人： James A. Gasbarro , Mark A. Horowitz , Richard M. Barth , Winston K. M. Lee , Wingyu Leung , Paul M. Farmwald
IPC分类号： G06F1/10 , G06F1/12 , G06F12/00 , G06F13/42 , G11C11/401 , G11C11/407 , H04L7/00
CPC分类号： G06F1/10 , G06F13/4217 , H04L7/0008
摘要： A bus system is described that minimizes clock-data skew. The bus system includes a data bus, a clockline and synchronization circuitry. The clockline has two clockline segments. Each clockline segment extends the entire length of the data bus and is joined to the other clockline segment by a turnaround at one end of the data bus. The clockline ensures that clock and data signals travel in the same direction. Synchronization circuitry within transmitting devices synchronizes data signals to be coupled onto the data bus with the clock signal used by other devices to receive the data.
摘要翻译：描述了最小化时钟数据偏移的总线系统。总线系统包括数据总线，时钟线和同步电路。时钟线有两个时钟线段。每个时钟线段延伸数据总线的整个长度，并通过数据总线一端的转向连接到另一个时钟线段。时钟线确保时钟和数据信号沿同一方向行进。发送设备内的同步电路将数据信号与其他设备使用的时钟信号同步到数据总线上，以接收数据。

3. 发明授权

US5268639A Testing timing parameters of high speed integrated circuit devices 失效
标题翻译：测试高速集成电路器件的时序参数
公开(公告)号：US5268639A
公开(公告)日：1993-12-07
申请号：US894525
申请日：1992-06-05
申请人： James A. Gasbarro , Mark A. Horowitz
发明人： James A. Gasbarro , Mark A. Horowitz
IPC分类号： G01R31/30 , G01R31/319 , G01R31/3193 , G11C29/02 , G11C29/50 , G01R31/00
CPC分类号： G11C29/022 , G01R31/31937 , G11C29/02 , G11C29/028 , G11C29/50 , G11C29/50012 , G01R31/30 , G01R31/3191 , G11C11/401
摘要： A method and apparatus for testing input and output parameters for high speed integrated circuit devices. An integrated circuit tester generates a receive clock and a transmit clock using a pair of pre-selected output pins. The integrated circuit tester adjusts the phase relation between the transmit clock and the receive clock. Special circuitry within the device under test compares input and output data to detect errors.
摘要翻译：一种用于测试高速集成电路器件的输入和输出参数的方法和装置。集成电路测试仪使用一对预选输出引脚产生接收时钟和发送时钟。集成电路测试仪调整发送时钟和接收时钟之间的相位关系。被测器件内的特殊电路将输入和输出数据进行比较，以检测错误。

4. 发明授权

US5357195A Testing set up and hold input timing parameters of high speed integrated circuit devices 失效
标题翻译：测试设置并保持高速集成电路器件的输入时序参数
公开(公告)号：US5357195A
公开(公告)日：1994-10-18
申请号：US109655
申请日：1993-08-20
申请人： James A. Gasbarro , Mark A. Horowitz
发明人： James A. Gasbarro , Mark A. Horowitz
IPC分类号： G01R31/30 , G01R31/319 , G01R31/3193 , G11C29/02 , G11C29/50 , G01R31/00
CPC分类号： G11C29/022 , G01R31/31937 , G11C29/02 , G11C29/028 , G11C29/50 , G11C29/50012 , G01R31/30 , G01R31/3191 , G11C11/401
摘要： A method and apparatus for testing input and output parameters for high speed integrated circuit devices. An integrated circuit tester generates a receive clock and a transmit clock using a pair of pre-selected output pins. The integrated circuit tester adjusts the phase relation between the transmit clock and the receive clock. Special circuitry within the device under test compares input and output data to detect errors.
摘要翻译：一种用于测试高速集成电路器件的输入和输出参数的方法和装置。集成电路测试仪使用一对预选输出引脚产生接收时钟和发送时钟。集成电路测试仪调整发送时钟和接收时钟之间的相位关系。被测器件内的特殊电路将输入和输出数据进行比较，以检测错误。

5. 发明授权

US5337285A Method and apparatus for power control in devices 失效
标题翻译：设备功率控制的方法和装置
公开(公告)号：US5337285A
公开(公告)日：1994-08-09
申请号：US65804
申请日：1993-05-21
申请人： Frederick A. Ware , James A. Gasbarro , John B. Dillon , Matthew M. Griffin , Richard M. Barth , Mark A. Horowitz
发明人： Frederick A. Ware , James A. Gasbarro , John B. Dillon , Matthew M. Griffin , Richard M. Barth , Mark A. Horowitz
IPC分类号： G06F1/32 , G11C5/14 , H03K19/00 , H03K19/0175 , G11C7/00
CPC分类号： G11C5/14
摘要： A power control circuit to minimize power consumption of CMOS circuits by disabling/enabling the clock input to the CMOS circuit. A phase locked loop (PLL) or delay locked loop (DLL) drives a capacitive load of the component and a dummy load comparable to the component load. A standby latch is provided to control the clock input to the component. In a standby state, the clock signal is not provided to the component but the PLL/DLL continues to operate, driving the dummy load. Thus, when it is desirable to power on the circuit, the standby latch is reset and the clock signal is provided to the component, thereby turning on the component with little latency.
摘要翻译：电源控制电路，通过禁止/使能CMOS电路的时钟输入来最小化CMOS电路的功耗。锁相环（PLL）或延迟锁定环（DLL）驱动组件的容性负载和与组件负载相当的虚拟负载。提供备用锁存器来控制对组件的时钟输入。在待机状态下，时钟信号不提供给组件，但PLL / DLL继续运行，驱动虚拟负载。因此，当期望对电路通电时，备用锁存器被复位，并且时钟信号被提供给部件，从而以很小的延迟打开部件。

6. 发明授权

US5325053A Apparatus for testing timing parameters of high speed integrated circuit devices 失效
标题翻译：用于测试高速集成电路器件的时序参数的装置
公开(公告)号：US5325053A
公开(公告)日：1994-06-28
申请号：US110094
申请日：1993-08-20
申请人： James A. Gasbarro , Mark A. Horowitz
发明人： James A. Gasbarro , Mark A. Horowitz
IPC分类号： G01R31/30 , G01R31/319 , G01R31/3193 , G11C29/02 , G11C29/50 , G01R31/00
CPC分类号： G11C29/022 , G01R31/31937 , G11C29/02 , G11C29/028 , G11C29/50 , G11C29/50012 , G01R31/30 , G01R31/3191 , G11C11/401
摘要： Apparatus for testing input and output parameters for high speed integrated circuit devices. An integrated circuit tester generates a receive clock and a transmit clock using a pair of pre-selected output pins. The integrated circuit tester adjusts the phase relation between the transmit clock and the receive clock. Special circuitry within the device under test compares input and output data to detect errors.
摘要翻译：用于测试高速集成电路设备的输入和输出参数的装置。集成电路测试仪使用一对预选输出引脚产生接收时钟和发送时钟。集成电路测试仪调整发送时钟和接收时钟之间的相位关系。被测器件内的特殊电路将输入和输出数据进行比较，以检测错误。

7. 发明授权

US5446696A Method and apparatus for implementing refresh in a synchronous DRAM system 失效
标题翻译：用于在同步DRAM系统中实现刷新的方法和装置
公开(公告)号：US5446696A
公开(公告)日：1995-08-29
申请号：US347770
申请日：1994-12-02
申请人： Frederick A. Ware , James A. Gasbarro , John B. Dillon , Michael P. Farmwald , Mark A. Horowitz , Matthew M. Griffin
发明人： Frederick A. Ware , James A. Gasbarro , John B. Dillon , Michael P. Farmwald , Mark A. Horowitz , Matthew M. Griffin
IPC分类号： G11C11/407 , G11C11/401 , G11C11/406 , G11G7/00
CPC分类号： G11C11/406
摘要： A synchronous DRAM system with internal refresh is controlled by a refresh signal issued by an oscillator or memory controller coupled to the DRAM. By locating the oscillator on the processor or memory controller better control of the frequency of refresh is achieved, particularly, as the signal can be derived from a crystal which is not sensitive to variations in operating conditions. The oscillator drives a refresh signal on a bus or signal line to the DRAM, such that the refresh address counter is incremented and the row identified by the refresh address counter is refreshed.
摘要翻译：具有内部刷新的同步DRAM系统由耦合到DRAM的振荡器或存储器控制器发出的刷新信号控制。通过将振荡器定位在处理器或存储器控制器上，可以更好地控制刷新频率，特别是可以从对操作条件变化不敏感的晶体导出信号。振荡器将总线或信号线上的刷新信号驱动到DRAM，使得刷新地址计数器递增，刷新地址计数器识别的行被刷新。

8. 发明申请

US20130255456A1 MICRO-CUTTING SYSTEMS FOR FORMING CUTS IN PRODUCTS 有权
标题翻译：微型切割系统在产品中形成
公开(公告)号：US20130255456A1
公开(公告)日：2013-10-03
申请号：US13901375
申请日：2013-05-23
申请人： Jeff Christian , Ryan Christian , James A. Gasbarro , Scott K. Boehmke , John Lippert
发明人： Jeff Christian , Ryan Christian , James A. Gasbarro , Scott K. Boehmke , John Lippert
IPC分类号： B26D5/20 , B26D5/00 , B26D7/06
CPC分类号： A61M25/0015 , A61M25/09 , A61M2025/09108 , B26D1/24 , B26D5/007 , B26D5/20 , B26D5/34 , B26D7/06 , B26D7/0683 , B26F1/0053 , B26F1/0061 , B26F1/0076 , Y10T83/0448 , Y10T83/051 , Y10T83/145 , Y10T83/173 , Y10T83/4458 , Y10T83/4463 , Y10T83/828 , Y10T83/8878
摘要： Micro-cutting machines for forming cuts in catheters, guidewires, and similar products, are disclosed, including a micro-cutting machine that can directly control the dimensions of the resultant beams being cut into products, and that can capture images of each cut for feedback control and accuracy verification.
摘要翻译：公开了用于在导管，导线和类似产品中形成切口的微切割机，包括可以直接控制被切割成产品的合成梁的尺寸的微切割机，并且可以捕获每个切割的图像以进行反馈控制和准确性验证。

9. 发明授权

US07793039B2 Interface for a semiconductor memory device and method for controlling the interface 有权
标题翻译：用于半导体存储器件的接口和用于控制接口的方法
公开(公告)号：US07793039B2
公开(公告)日：2010-09-07
申请号：US12349485
申请日：2009-01-06
申请人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarro , David Nguyen
发明人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarro , David Nguyen
IPC分类号： G06F12/00
CPC分类号： G11C7/22 , G11C7/1006 , G11C7/12 , G11C8/12 , G11C8/18 , G11C11/406 , G11C11/40611 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C2207/2218
摘要： A semiconductor memory device includes a memory core, a first interface to receive write data from a first set of interconnect resources, and a second interface, separate from the first interface, to receive from a second set of interconnect resources a column address and a first code. The column address is associated with the write data and identifies a column of the memory core in which to store the write data. The first code indicates whether the write data is selectively masked by data mask information. If the first code indicates that the write data is selectively masked, the second interface is to receive data mask information specifying whether to selectively write portions of the write data to the memory core.
摘要翻译：半导体存储器件包括存储器核，从第一组互连资源接收写数据的第一接口和与第一接口分开的第二接口，以从第二组互连资源接收列地址和第一码。列地址与写入数据相关联，并标识存储写入数据的存储器核心的列。第一代码指示写数据是否被数据掩码信息选择性地屏蔽。如果第一代码指示写入数据被选择性地屏蔽，则第二接口将接收指定是否选择性地将写数据的部分写入存储器核的数据掩码信息。

10. 发明申请

US20120173810A1 Method and Apparatus for Indicating Mask Information 有权
标题翻译：用于指示面罩信息的方法和装置
公开(公告)号：US20120173810A1
公开(公告)日：2012-07-05
申请号：US13421701
申请日：2012-03-15
申请人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarro , David Nguyen
发明人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarro , David Nguyen
IPC分类号： G06F12/00
CPC分类号： G11C7/22 , G11C7/1006 , G11C7/12 , G11C8/12 , G11C8/18 , G11C11/406 , G11C11/40611 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C2207/2218
摘要： An apparatus for controlling a dynamic random access memory (DRAM), the apparatus comprising an interface to transmit, over a first plurality of wires, to the DRAM a first code to indicate that first data is to be written to the DRAM and a column address to indicate a column location of a memory core in the DRAM where the first data is to be written. The interface is further to transmit a second code to indicate whether mask information for the first data will be sent to the DRAM. If the second code indicates that mask information will be sent, a portion of the column address and a portion of the mask information are sent after the second code is sent. The interface is further to transmit to the DRAM, over a second plurality of wires separate from the first plurality of wires, the first data.
摘要翻译：一种用于控制动态随机存取存储器（DRAM）的装置，该装置包括一个接口，用于在第一组多条引线上向DRAM发送一个第一代码，以指示第一个数据要写入DRAM，列地址以指示要写入第一数据的DRAM中的存储器核的列位置。该接口还用于发送第二代码以指示是否将第一数据的掩码信息发送到DRAM。如果第二代码指示将发送掩码信息，则在发送第二代码之后发送列地址的一部分和掩码信息的一部分。接口进一步通过与第一多个电线分开的第二多个电线将DRAM发送到第一数据。

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