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    • 1. 发明授权
    • Method of fabricating a self-aligned DMOS transistor device using SiC
and spacers
    • 使用SiC和间隔物制造自对准DMOS晶体管器件的方法
    • US5510281A
    • 1996-04-23
    • US406440
    • 1995-03-20
    • Mario GhezzoTat-Sing P. ChowJames W. KretchmerRichard J. SaiaWilliam A. Hennessy
    • Mario GhezzoTat-Sing P. ChowJames W. KretchmerRichard J. SaiaWilliam A. Hennessy
    • H01L21/04H01L29/24H01L29/423H01L29/45H01L29/78H01L21/265
    • H01L29/1608H01L29/42376H01L29/4238H01L29/45H01L29/66068H01L29/7802
    • A method for fabricating a semiconductor device includes patterning a refractory dielectric layer over a semiconductor layer of a first conductivity type; conformally depositing a first spacer layer over the patterned refractory dielectric layer and the semiconductor layer; patterning the first spacer layer to leave a first spacer adjacent to an edge of the patterned refractory dielectric layer; implanting ions of a second conductivity type to form a base region in the semiconductor layer; conformally depositing a second spacer layer over the patterned refractory dielectric layer and the semiconductor layer; patterning the second spacer layer to leave a second spacer adjacent to an edge of the first spacer; implanting ions of the first conductivity type to form a source region in the base region; removing the first and second spacers; applying a gate insulator layer over at least a portion of the semiconductor layer; conformally depositing a gate electrode layer over the gate insulator layer and the semiconductor layer; and patterning the gate electrode layer to form a gate electrode portion adjacent to an edge of the patterned refractory dielectric layer. Preferably the step of conformally depositing the gate electrode layer includes depositing an electrically conductive layer having the same thickness as a combined width of the first and second spacers. In one embodiment the semiconductor layer includes silicon carbide, the patterned refractory dielectric layer includes silicon dioxide, the spacers include silicon nitride, and the gate electrode layer includes polysilicon.
    • 一种用于制造半导体器件的方法包括在第一导电类型的半导体层上图形化难熔电介质层; 在图案化的难熔电介质层和半导体层上共形沉积第一间隔层; 图案化第一间隔层以留下邻近图案化耐火介电层的边缘的第一间隔物; 注入第二导电类型的离子以在半导体层中形成基极区; 在图案化的耐火介电层和半导体层上共形沉积第二间隔层; 图案化第二间隔层以留下与第一间隔物的边缘相邻的第二间隔物; 注入第一导电类型的离子以在基区中形成源区; 去除所述第一和第二间隔件; 在所述半导体层的至少一部分上施加栅极绝缘体层; 在所述栅极绝缘体层和所述半导体层上共形沉积栅电极层; 以及图案化栅极电极层以形成邻近图案化耐火介电层的边缘的栅电极部分。 优选地,共形沉积栅极电极层的步骤包括沉积具有与第一和第二间隔物的组合宽度相同的厚度的导电层。 在一个实施例中,半导体层包括碳化硅,图案化的难熔电介质层包括二氧化硅,间隔物包括氮化硅,并且栅电极层包括多晶硅。
    • 4. 发明授权
    • Methods for forming and positioning moldable permanent magnets on
electromagnetically actuated microfabricated components
    • 在电磁致动的微制造部件上形成和定位成型永久磁铁的方法
    • US5472539A
    • 1995-12-05
    • US254725
    • 1994-06-06
    • Richard J. SaiaKevin M. DurocherThomas B. GorczycaMario Ghezzo
    • Richard J. SaiaKevin M. DurocherThomas B. GorczycaMario Ghezzo
    • H01H50/00B32B31/28
    • H01H50/005H02K99/00H01H2050/007
    • A low temperature batch method for forming and positioning permanent magnets on electromagnetically actuated micro-fabricated components, such as electrical switches employs a first adhesive, such as a Siltem/epoxy blend of an epoxy resin and a siloxane polyimide polymer, to releasably attach a mold layer of Kapton polyimide to a substrate, which may be the movable portion of a micromechanical structure, or a precursor to such movable portion. A well-shape cavity is formed in the mold layer, and filled with a slurry of rare earth NdFeB magnetic particles suspended in a second adhesive, which is cured to form the body of a magnet. The second adhesive is an SPI/epoxy blend, also of an epoxy resin and a siloxane polyimide polymer, but with a greater adhesion strength and a higher temperature softening point compared to the Siltem/epoxy blend. The entire structure is heated, and the mold layer is pulled off the substrate, while the body of magnetic material remains firmly attached. Selective etchants may be subsequently employed to remove metal sacrificial layers, while the NdFeB magnetic particles are protected from attack by the etchant by being effectively encased in plastic.
    • 用于在诸如电气开关的电磁致动微制造部件上形成和定位永磁体的低温分批方法采用第一粘合剂,例如环氧树脂的Siltem /环氧共混物和硅氧烷聚酰亚胺聚合物,以可释放地附接模具 Kapton聚酰亚胺层可以是基底,其可以是微机械结构的可移动部分,或者是可移动部分的前体。 在模具层中形成良好的形状的空腔,并填充悬浮在第二粘合剂中的稀土NdFeB磁性颗粒的浆料,其被固化以形成磁体的主体。 第二种粘合剂是SPI /环氧共混物,也是环氧树脂和硅氧烷聚酰亚胺聚合物,但是与Siltem /环氧树脂共混物相比具有更大的粘合强度和更高的温度软化点。 整个结构被加热,并且模具层被拉离基板,而磁性材料的主体保持牢固地附着。 随后可以选择性蚀刻剂去除金属牺牲层,同时通过被有效地包裹在塑料中来保护NdFeB磁性颗粒免受蚀刻剂的侵蚀。
    • 5. 发明授权
    • Current interrupting device using micromechanical components
    • 电流中断装置采用微机械元件
    • US5430597A
    • 1995-07-04
    • US313
    • 1993-01-04
    • Bharat S. BagepalliMario GhezzoRichard J. SaiaImdad Imam
    • Bharat S. BagepalliMario GhezzoRichard J. SaiaImdad Imam
    • H01H9/40H01H59/00H01H71/12H01H73/00
    • H01H59/0009H01H2071/008H01H71/123H01H9/40
    • A circuit interruption device having a plurality of micromechanical switches mounted on a substrate in a parallel-series array. The array includes a plurality of line branches connected in parallel in a circuit line. Each of the line branches has at least two of the switches serially connected therein. The micromechanical switches each has a pair of contacts formed on the substrate, a bridging contact movably formed on the substrate, and an actuator for causing the bridging contact to move in and out of contact with the contacts. The bridging contact can be either a member slidably disposed in a channel formed on the substrate or member attached to an end of a cantilever having its other end attached to the substrate. The actuator is controlled by a trip device which is also mounted on the substrate. The trip device senses the current in the circuit line and causes the switches to open when a predetermined level of current in the line is exceeded.
    • 一种电路中断装置,具有以平行阵列阵列安装在基板上的多个微机械开关。 阵列包括在电路线中并联连接的多个线分支。 每个线路分支具有串联连接在其中的至少两个开关。 微机械开关各自具有形成在基板上的一对触点,可移动地形成在基板上的桥接触头和用于使桥接触点移动进入和断开与触点接触的致动器。 桥接接触可以是可滑动地设置在形成在基底上的通道中的构件或附接到其另一端附接到基底的悬臂的端部的构件。 致动器由也安装在基板上的跳闸装置控制。 跳闸装置感测电路线路中的电流,并且当超过线路中的预定电流电流时使开关断开。
    • 10. 发明授权
    • Method of making a thin film transistor structure with improved
source/drain contacts
    • 制造具有改善的源极/漏极触点的薄膜晶体管结构的方法
    • US5362660A
    • 1994-11-08
    • US977967
    • 1992-11-18
    • Robert F. KwasnickGeorge E. PossinDavid E. HoldenRichard J. Saia
    • Robert F. KwasnickGeorge E. PossinDavid E. HoldenRichard J. Saia
    • H01L21/3213H01L21/336H01L29/45H01L21/265
    • H01L29/66765H01L21/32139H01L29/458Y10S438/97
    • Minimum line spacing is reduced and line spacing uniformity is increased in thin film transistors by employing source/drain metallization having a first relatively thin layer of a first conductor and a second relatively thick layer of a second conductor. The second conductor is selected to be one which may be preferentially etched in the presence of the first conductor whereby the first conductor acts as an etch stop for the etchant used to pattern the second conductor portion of the source/drain metallization. This etching is preferably done using dry etching. Dry etching typically provides substantially better control of line width than wet etching. The etching of the second conductor can be done with a dry etch process which etches the photoresist at substantially the same rate as the second conductor whereby the second conductor is provided with a sidewall slope of substantially 45.degree. which improves the quality of passivation provided by subsequent deposition of a conformal passivating layer.
    • 通过采用具有第一相对薄的第一导体层和第二相对较厚的第二导体层的源极/漏极金属化,薄膜晶体管中的最小线间距减小,并且线间隔均匀性增加。 第二导体被选择为可以在第一导体存在的情况下优先蚀刻的导体,由此第一导体充当用于图案化源极/漏极金属化的第二导体部分的蚀刻剂的蚀刻停止。 该蚀刻优选使用干蚀刻进行。 干蚀刻通常比湿式蚀刻提供对线宽度的更好的控制。 第二导体的蚀刻可以通过干法蚀刻工艺进行,该蚀刻工艺以基本上与第二导体相同的速率蚀刻光致抗蚀剂,由此第二导体设置有大致为45°的侧壁斜率,这提高了后续提供的钝化质量 共形钝化层的沉积。