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1. 发明授权

US06528405B1 Enhancement mode RF device and fabrication method 失效
标题翻译：增强型RF器件及其制造方法
公开(公告)号：US06528405B1
公开(公告)日：2003-03-04
申请号：US09506844
申请日：2000-02-18
申请人： Marino J. Martinez , Ernest Schirmann , Olin L. Hartin , Elizabeth C. Glass , Julio C. Costa
发明人： Marino J. Martinez , Ernest Schirmann , Olin L. Hartin , Elizabeth C. Glass , Julio C. Costa
IPC分类号： H01L2128
CPC分类号： H01L29/66462 , H01L21/28587 , H01L29/7784
摘要： An enhancement mode RF device and method of fabrication includes a stack of compound semiconductor layers, including a central layer defining a device channel, a doped cap layer, and a buffer epitaxially grown on a substrate. Source and drain implant areas, extending at least into the buffer, are formed to define an implant free area in the device channel between the source and drain. Source and drain metal contacts are positioned on an upper surface of the central layer. Several layers of insulation and dielectric are positioned over the device and a gate opening is formed and filled with gate metal. During epitaxial growth, the doped cap layer is tailored with a thickness and a doping to optimize channel performance including gate-drain breakdown voltage and channel resistance.
摘要翻译：增强型RF器件和制造方法包括：化合物半导体层的堆叠，包括限定器件沟道的中心层，掺杂的覆盖层和在衬底上外延生长的缓冲层。形成至少延伸到缓冲器中的源极和漏极注入区域，以在源极和漏极之间的器件沟道中限定无植入区域。源极和漏极金属触点位于中心层的上表面上。绝缘和电介质的几层位于器件上方，并形成栅极开口并填充栅极金属。在外延生长期间，掺杂的覆盖层是通过厚度和掺杂来调整的，以优化沟道性能，包括栅 - 漏击穿电压和沟道电阻。

2. 发明授权

US07345545B2 Enhancement mode transceiver and switched gain amplifier integrated circuit 有权
标题翻译：增强型收发器和开关增益放大器集成电路
公开(公告)号：US07345545B2
公开(公告)日：2008-03-18
申请号：US11092070
申请日：2005-03-28
申请人： Elizabeth C. Glass , Olin L. Hartin , Ngai Ming Lau , Neil T. Tracht
发明人： Elizabeth C. Glass , Olin L. Hartin , Ngai Ming Lau , Neil T. Tracht
IPC分类号： H03F3/16
CPC分类号： H03G1/0088
摘要： Methods and apparatus are provided for RF switches (504, 612) integrated in a monolithic RF transceiver IC (500) and switched gain amplifier (600). Multi-gate n-channel enhancement mode FETs (50, 112, 114, Q1-3, Q4-6) are used with single gate FETs (150), resistors (Rb, Rg, Re, R1-R17) and capacitors (C1-C3) formed by the same manufacturing process. The multiple gates (68) of the FETs (50, 112, 114, Q1-3, Q4-6) are parallel coupled, spaced-apart and serially arranged between source (72) and drain (76). When used in pairs (112, 114) to form a switch (504) for a transceiver (500) each FET has its source (74) coupled to an antenna RF I/O port (116, 501) and drains coupled respectively to second and third RF I/O ports (118, 120; 507, 521) leading to the receiver side (530) or transmitter side (532) of the transceiver (500). The gates (136, 138) are coupled to control ports (122, 124; 503, 505; 606, 608). When used in pairs (Q1-3, Q4-6) to form a variable switched attenuator, the first FET (Q1-3) is a pass device and the second FET (Q4-6) is a shunt device that respectively bridge two series resistors (R1, R2) and block a shunt resistor (R3) of a T-type attenuator.
摘要翻译：为集成在单片RF收发器IC（500）和开关增益放大器（600）中的RF开关（504,612）提供了方法和装置。多栅极n沟道增强型FET（50,112,114，Q 1-3，Q 4-6）与单栅极FET（150），电阻器（Rb，Rg，Re，R 1 -R 17）和通过相同制造工艺形成的电容器（C 1 -C 3）。 FET（50,112,114，Q1-3，Q4-6）的多个栅极（68）被平行耦合，间隔开并且串联地布置在源极（72）和漏极（76）之间。当成对使用（112,114）形成用于收发器（500）的开关（504）时，每个FET的源极（74）耦合到天线RF I / O端口（116,501），并且分别耦合到第二以及通向收发器（500）的接收机侧（530）或发射机侧（532）的第三RF I / O端口（118,120; 507,521）。门（136,138）被耦合到控制端口（122,124; 503,505; 606,608）。当成对使用（Q 1 - 3，Q 4 - 6）以形成可变开关衰减器时，第一FET（Q1-3）是通过器件，第二FET（Q 4 - 6）是分流器件，分别桥接两个串联电阻（R 1，R 2）并阻塞T型衰减器的分流电阻（R 3）。

3. 发明授权

US07504677B2 Multi-gate enhancement mode RF switch and bias arrangement 有权
标题翻译：多栅极增强模式RF开关和偏置布置
公开(公告)号：US07504677B2
公开(公告)日：2009-03-17
申请号：US11092264
申请日：2005-03-28
申请人： Elizabeth C. Glass , Olin L. Hartin , Neil T. Tracht
发明人： Elizabeth C. Glass , Olin L. Hartin , Neil T. Tracht
IPC分类号： H01L29/80 , H01L21/337
CPC分类号： H01L27/0605 , H01L23/4824 , H01L29/42316 , H01L29/7786 , H01L2924/0002 , H01L2924/3011 , H04B1/48 , H01L2924/00
摘要： Methods and apparatus are provided for RF switches (100, 200). In a preferred embodiment, the apparatus comprises one or more multi-gate n-channel enhancement mode FET transistors (50, 112, 114). When used in pairs (112, 114) each has its source (74, 133) coupled to a first common RF I/O port (116) and drains coupled respectively to second and third RF I/O ports (118, 120), and gates (136, 138), coupled respectively to first and second control terminals (122, 124). The multi-gate regions (66, 68) of the FETs (50) are parallel coupled, spaced-apart and serially arranged between source (72) and drain (76). Lightly doped n-regions (Ldd, Lds) are provided serially arranged between the spaced-apart multi-gate regions (66, 68), the lightly doped n-regions (Ldd, Lds) being separated by more heavily doped n-regions (84). Bias resistances (132, 134) are provided between the sources (72, 133) and control terminals (122, 124) so as to provide a DC path between the control terminals (122, 124) that maintains the source (72, 133) voltage at the proper bias potential for enhancement mode operation.
摘要翻译：提供了用于RF开关（100,200）的方法和装置。在优选实施例中，该装置包括一个或多个多栅极n沟道增强型FET晶体管（50,112,114）。当成对使用时，每个都具有耦合到第一公共RF I / O端口（116）的源极（74,133）和分别耦合到第二和第三RF I / O端口（118,120）的漏极，和分别耦合到第一和第二控制端（122,124）的门（136,138）。 FET（50）的多栅极区域（66,68）平行耦合，间隔开并且串联地布置在源极（72）和漏极（76）之间。轻度掺杂的n区（Ldd，Lds）被串行地布置在间隔开的多栅极区（66,68）之间，轻掺杂的n-区（Ldd，Lds）被更重掺杂的n区分离（ 84）。偏置电阻（132,134）设置在源极（72,133）和控制端子（122,124）之间，以便在维持源极（72,133）和控制端子（122,124）之间提供DC路径，电压处于适当的偏置电位，用于增强模式操作。

4. 发明授权

US06479843B2 Single supply HFET with temperature compensation 有权
标题翻译：单电源HFET具有温度补偿功能
公开(公告)号：US06479843B2
公开(公告)日：2002-11-12
申请号：US09559791
申请日：2000-04-27
申请人： Jenn-Hwa Huang , Elizabeth C. Glass , Olin Hartin , Wendy L. Valentine , Julio Costa
发明人： Jenn-Hwa Huang , Elizabeth C. Glass , Olin Hartin , Wendy L. Valentine , Julio Costa
IPC分类号： H01L21338
CPC分类号： H01L21/8252 , H01L27/0248 , H01L27/0605 , H03F1/301 , H03K17/145
摘要： A method of fabricating apparatus, and the apparatus, for providing low voltage temperature compensation in a single power supply HFET including a stack of epitaxially grown compound semiconductor layers with an HFET formed in the stack. A Schottky diode is formed in the stack adjacent the HFET during the formation of the HFET. The HFET and the Schottky diode are formed simultaneously, with a portion of one of the layers of metal forming the gate of the HFET being positioned in contact with a layer of the stack having a low bandgap (e.g. less than 0.8 eV) to provide a turn-on voltage for the Schottky diode of less than 1.8 Volts. The Schottky diode is connected to the gate contact of the HFET by a gate circuit to compensate for changes in current loading in the gate circuit with changes in temperature.
摘要翻译：一种制造装置的方法和装置，用于在单个电源HFET中提供低电压温度补偿，所述单电源HFET包括在叠层中形成的具有HFET的外延生长的化合物半导体层的堆叠。在形成HFET期间，在与HFET相邻的堆叠中形成肖特基二极管。 HFET和肖特基二极管同时形成，形成HFET的栅极的一层金属的一部分定位成与具有低带隙（例如小于0.8eV）的堆叠层接触，以提供肖特基二极管的导通电压小于1.8伏。肖特基二极管通过栅极电路连接到HFET的栅极接触，以补偿栅极电路中随着温度变化的电流负载的变化。

5. 发明授权

US07821102B2 Power transistor featuring a double-sided feed design and method of making the same 有权
标题翻译：功率晶体管采用双面进料设计和制作方法
公开(公告)号：US07821102B2
公开(公告)日：2010-10-26
申请号：US11671035
申请日：2007-02-05
申请人： Dragan Zupac , Sandra J. Wipf , Theresa M. Keller , Elizabeth C. Glass
发明人： Dragan Zupac , Sandra J. Wipf , Theresa M. Keller , Elizabeth C. Glass
IPC分类号： H01L27/082 , H01L29/70
CPC分类号： H01L29/73 , H01L23/4824 , H01L24/13 , H01L29/0692 , H01L29/41708 , H01L29/42304 , H01L29/7322 , H01L2224/16 , H01L2924/19043 , H01L2924/30107
摘要： A power transistor (210) comprises a plurality of unit cell devices (212), a base contact configuration, an emitter contact configuration, and a collector contact configuration. The plurality of unit cell devices is arranged along an axis (194), each unit cell device including base (80), emitter (82), and collector (84) portions. The base contact configuration includes (i) a first base feed (150) coupled to the base portion of each unit cell device via a first end of at least one base finger (154) associated with a corresponding unit cell device and (ii) a second base feed (152) coupled to the base portion of each unit cell device via an opposite end of the at least one base finger associated with the corresponding unit cell device. The emitter contact configuration includes (i) a first emitter feed (172) coupled to the emitter portion of each unit cell device via a first end of an emitter metallization (176) associated with a corresponding unit cell device and (ii) a second emitter feed (174) coupled to the emitter portion of each unit cell device via an opposite end of the emitter metallization associated with the corresponding unit cell device. The collector contact configuration includes a collector feed (188) coupled to the collector portion of each unit cell device.
摘要翻译：功率晶体管（210）包括多个单位电池器件（212），基极触点配置，发射极触点配置和集电极触点配置。多个单电池器件沿轴线（194）布置，每个单元电池器件包括基极（80），发射极（82）和集电极（84）部分。基本接触配置包括：（i）经由与相应的单位电池器件相关联的至少一个基本手指（154）的第一端耦合到每个单元电池器件的基座部分的第一基本馈电（150）和（ii）第二基本馈送（152），其经由与所述对应的单元设备相关联的所述至少一个基本指的相对端耦合到每个单元单元设备的基本部分。发射极接触配置包括：（i）经由与相应的单位电池器件相关联的发射极金属化（176）的第一端耦合到每个单位电池器件的发射极部分的第一发射极馈电（172）和（ii）第二发射极馈电（174）经由与相应的单位电池器件相关联的发射极金属化的相对端耦合到每个单位电池器件的发射极部分。集电极接触配置包括耦合到每个单位电池器件的集电极部分的集电极馈送（188）。

6. 发明申请

US20090212374A1 SPACE EFFICIENT INTEGRATRED CIRCUIT WITH PASSIVE DEVICES 有权
标题翻译：空间有效的集成电路与被动设备
公开(公告)号：US20090212374A1
公开(公告)日：2009-08-27
申请号：US12037280
申请日：2008-02-26
申请人： Jenn Hwa Huang , Elizabeth C. Glass
发明人： Jenn Hwa Huang , Elizabeth C. Glass
IPC分类号： H01L27/06
CPC分类号： H01L27/08 , H01L23/5223 , H01L23/5227 , H01L23/5228 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A multimodal integrated circuit (IC) is provided, comprising, first (74) and second (76) semiconductor (SC) devices, and first (78) and second (80) integrated passive devices (IPDs) coupled, respectively, to the first (74) and second (76) SC devices, wherein the first IPD (78) overlies the second SC device (76) and the second IPD (80) overlies the first SC device (74) chosen such that the underlying SC device (74, 76) is not active at the same time as its overlying IPD (80, 78). By placing the IPDs (78, 80) over the SC devices (76, 74) a compact IC layout is obtained. Since the overlying IPD (78, 80) and underlying SC (76, 74) are not active at the same time, undesirable cross-talk (68, 69) between the IPDs (78, 80) and the SC devices (76, 74) is avoided. This arrangement applies to any IC having multiple signal paths (RF1, RF2) where the IPDs (78, 80) of a first path (RF1, RF2) may be placed over the SC devices (76, 74) of a second path (RF2, RF1) not active at the same time. This is especially useful with high frequencies ICs.
摘要翻译：提供了一种多模式集成电路（IC），其包括第一（74）和第二（76）半导体（SC）器件以及第一（78）和第二（80）集成无源器件（IPD），分别耦合到第一（74）和第二（76）个SC设备，其中所述第一IPD（78）覆盖所述第二SC设备（76），并且所述第二IPD（80）覆盖所选择的所述第一SC设备（74），使得所述下面的SC设备，76）在上层IPD的同时不起作用（80,78）。通过将IPD（78,80）放置在SC设备（76,74）上，可以获得紧凑的IC布局。由于上覆IPD（78,80）和底层SC（76,74）同时不起作用，IPD（78,80）与SC设备（76,74）之间的不期望的串扰（68,69））。这种布置适用于具有多个信号路径（RF1，RF2）的任何IC，其中第一路径（RF1，RF2）的IPD（78,80）可以放置在第二路径（RF2，RF2）的SC设备（76,74）上，RF1）不同时激活。这对于高频IC尤其有用。

7. 发明授权

US07868393B2 Space efficient integrated circuit with passive devices 有权
标题翻译：空间高效集成电路与无源器件
公开(公告)号：US07868393B2
公开(公告)日：2011-01-11
申请号：US12037280
申请日：2008-02-26
申请人： Jenn Hwa Huang , Elizabeth C. Glass
发明人： Jenn Hwa Huang , Elizabeth C. Glass
IPC分类号： H01L27/06
CPC分类号： H01L27/08 , H01L23/5223 , H01L23/5227 , H01L23/5228 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A multimodal integrated circuit (IC) is provided, comprising, first (74) and second (76) semiconductor (SC) devices, and first (78) and second (80) integrated passive devices (IPDs) coupled, respectively, to the first (74) and second (76) SC devices, wherein the first IPD (78) overlies the second SC device (76) and the second IPD (80) overlies the first SC device (74) chosen such that the underlying SC device (74, 76) is not active at the same time as its overlying IPD (80, 78). By placing the IPDs (78, 80) over the SC devices (76, 74) a compact IC layout is obtained. Since the overlying IPD (78, 80) and underlying SC (76, 74) are not active at the same time, undesirable cross-talk (68, 69) between the IPDs (78, 80) and the SC devices (76, 74) is avoided. This arrangement applies to any IC having multiple signal paths (RF1, RF2) where the IPDs (78, 80) of a first path (RF1, RF2) may be placed over the SC devices (76, 74) of a second path (RF2, RF1) not active at the same time. This is especially useful with high frequencies ICs.
摘要翻译：提供了一种多模式集成电路（IC），其包括第一（74）和第二（76）半导体（SC）器件以及第一（78）和第二（80）集成无源器件（IPD），分别耦合到第一（74）和第二（76）个SC设备，其中所述第一IPD（78）覆盖所述第二SC设备（76），并且所述第二IPD（80）覆盖所选择的所述第一SC设备（74），使得所述下面的SC设备，76）在上层IPD的同时不起作用（80,78）。通过将IPD（78,80）放置在SC设备（76,74）上，可以获得紧凑的IC布局。由于上覆IPD（78,80）和底层SC（76,74）同时不起作用，IPD（78,80）与SC设备（76,74）之间的不期望的串扰（68,69））。这种布置适用于具有多个信号路径（RF1，RF2）的任何IC，其中第一路径（RF1，RF2）的IPD（78,80）可以放置在第二路径（RF2，RF2）的SC设备（76,74）上，RF1）不同时激活。这对于高频IC尤其有用。

8. 发明申请

US20080150082A1 POWER TRANSISTOR FEATURING A DOUBLE-SIDED FEED DESIGN AND METHOD OF MAKING THE SAME 有权
标题翻译：功率晶体管具有双面进料设计及其制造方法
公开(公告)号：US20080150082A1
公开(公告)日：2008-06-26
申请号：US11671035
申请日：2007-02-05
申请人： Dragan Zupac , Sandra J. Wipf , Theresa M. Keller , Elizabeth C. Glass
发明人： Dragan Zupac , Sandra J. Wipf , Theresa M. Keller , Elizabeth C. Glass
IPC分类号： H01L27/082
CPC分类号： H01L29/73 , H01L23/4824 , H01L24/13 , H01L29/0692 , H01L29/41708 , H01L29/42304 , H01L29/7322 , H01L2224/16 , H01L2924/19043 , H01L2924/30107
摘要： A power transistor (210) comprises a plurality of unit cell devices (212), a base contact configuration, an emitter contact configuration, and a collector contact configuration. The plurality of unit cell devices is arranged along an axis (194), each unit cell device including base (80), emitter (82), and collector (84) portions. The base contact configuration includes (i) a first base feed (150) coupled to the base portion of each unit cell device via a first end of at least one base finger (154) associated with a corresponding unit cell device and (ii) a second base feed (152) coupled to the base portion of each unit cell device via an opposite end of the at least one base finger associated with the corresponding unit cell device. The emitter contact configuration includes (i) a first emitter feed (172) coupled to the emitter portion of each unit cell device via a first end of an emitter metallization (176) associated with a corresponding unit cell device and (ii) a second emitter feed (174) coupled to the emitter portion of each unit cell device via an opposite end of the emitter metallization associated with the corresponding unit cell device. The collector contact configuration includes a collector feed (188) coupled to the collector portion of each unit cell device.
摘要翻译：功率晶体管（210）包括多个单位电池器件（212），基极触点配置，发射极触点配置和集电极触点配置。多个单电池器件沿轴线（194）布置，每个单元电池器件包括基极（80），发射极（82）和集电极（84）部分。基本接触配置包括：（i）经由与相应的单位电池器件相关联的至少一个基本手指（154）的第一端耦合到每个单元电池器件的基座部分的第一基本馈电（150）和（ii）第二基本馈送（152），其经由与所述对应的单元设备相关联的所述至少一个基本指的相对端耦合到每个单元单元设备的基本部分。发射极接触配置包括：（i）经由与相应的单位电池器件相关联的发射极金属化（176）的第一端耦合到每个单位电池器件的发射极部分的第一发射极馈电（172）和（ii）第二发射极馈电（174）经由与相应的单位电池器件相关联的发射极金属化的相对端耦合到每个单位电池器件的发射极部分。集电极接触配置包括耦合到每个单位电池器件的集电极部分的集电极馈送（188）。

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