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    • 1. 发明申请
    • ELUT: ENHANCED LOOK-UP TABLE SIGNAL PROCESSING
    • ELUT:增强查看表信号处理
    • US20090228737A1
    • 2009-09-10
    • US12045033
    • 2008-03-10
    • MOIS P. NAVONYossi KreininEmmanuel SixouRoman Sajman
    • MOIS P. NAVONYossi KreininEmmanuel SixouRoman Sajman
    • G06F15/76G06F9/30G06F1/04
    • G06F9/3001G06F9/30098
    • An electronic device including an array of addressable registers storing data. An input register connected to the array stores an input command parameter (e.g an opcode of a command) and its associated operands in one or more input registers connected to the addressable register array. A single instance of a command accesses the at least one register of the array. Based on the input command parameter, the command for all of the address operands: reads a datum of the data previously stored in at least one register, updates the datum thereby producing an updated datum, and writes the updated datum into at least one register. The command has multiple address operands referencing the one or more registers and supports two or more of the address operands being identical. The device includes logic circuitry which provides a logical output signal to the processing circuitry indicating which, if any, of the address operands are identical. The processing circuitry based on the logical output, processes first any identical address operands prior to writing the updated datum into the at least one register so that a new instance of the command begins processing by the processing circuitry on a consecutive clock pulse and the command throughput is one command per clock pulse.
    • 一种包括存储数据的可寻址寄存器阵列的电子设备。 连接到阵列的输入寄存器在连接到可寻址寄存器阵列的一个或多个输入寄存器中存储输入命令参数(例如命令的操作码)及其相关联的操作数。 命令的单个实例访问阵列的至少一个寄存器。 基于输入命令参数,所有地址操作数的命令:读取先前存储在至少一个寄存器中的数据的数据,更新数据,从而产生更新的数据,并将更新的数据写入至少一个寄存器。 该命令具有引用一个或多个寄存器的多个地址操作数,并支持两个或多个地址操作数相同。 该装置包括向处理电路提供逻辑输出信号的逻辑电路,指示地址操作数中的哪一个(如果有的话)是相同的。 基于逻辑输出的处理电路在将更新的数据写入至少一个寄存器之前首先处理任何相同的地址操作数,使得命令的新实例在处理电路上以连续的时钟脉冲和指令吞吐量开始处理 每个时钟脉冲是一个命令。
    • 2. 发明授权
    • ELUT: enhanced look-up table signal processing
    • ELUT:增强查询表信号处理
    • US08300058B2
    • 2012-10-30
    • US12045033
    • 2008-03-10
    • Mois P. NavonYossi KreininEmmanuel SixouRoman Sajman
    • Mois P. NavonYossi KreininEmmanuel SixouRoman Sajman
    • G09G5/36G06F13/14
    • G06F9/3001G06F9/30098
    • An electronic device including an array of addressable registers storing data. An input register connected to the array stores an input command parameter (e.g an opcode of a command) and its associated operands in one or more input registers connected to the addressable register array. A single instance of a command accesses the at least one register of the array. Based on the input command parameter, the command for all of the address operands: reads a datum of the data previously stored in at least one register, updates the datum thereby producing an updated datum, and writes the updated datum into at least one register. The command has multiple address operands referencing the one or more registers and supports two or more of the address operands being identical. The device includes logic circuitry which provides a logical output signal to the processing circuitry indicating which, if any, of the address operands are identical. The processing circuitry based on the logical output, processes first any identical address operands prior to writing the updated datum into the at least one register so that a new instance of the command begins processing by the processing circuitry on a consecutive clock pulse and the command throughput is one command per clock pulse.
    • 一种包括存储数据的可寻址寄存器阵列的电子设备。 连接到阵列的输入寄存器在连接到可寻址寄存器阵列的一个或多个输入寄存器中存储输入命令参数(例如命令的操作码)及其相关联的操作数。 命令的单个实例访问阵列的至少一个寄存器。 基于输入命令参数,所有地址操作数的命令:读取先前存储在至少一个寄存器中的数据的数据,更新数据,从而产生更新的数据,并将更新的数据写入至少一个寄存器。 该命令具有引用一个或多个寄存器的多个地址操作数,并支持两个或多个地址操作数相同。 该装置包括向处理电路提供逻辑输出信号的逻辑电路,指示地址操作数中的哪一个(如果有的话)是相同的。 基于逻辑输出的处理电路在将更新的数据写入至少一个寄存器之前首先处理任何相同的地址操作数,使得命令的新实例在处理电路上以连续的时钟脉冲和指令吞吐量开始处理 每个时钟脉冲是一个命令。
    • 3. 发明申请
    • Scheduling of Multiple Tasks in a System Including Multiple Computing Elements
    • 在包含多个计算元素的系统中调度多个任务
    • US20090300629A1
    • 2009-12-03
    • US12131173
    • 2008-06-02
    • Mois NavonElchanan RushinekEmmanuel SixouArkady PannYossi Kreinin
    • Mois NavonElchanan RushinekEmmanuel SixouArkady PannYossi Kreinin
    • G06F9/44
    • G06F9/4881G06F2209/483
    • A method for controlling parallel process flow in a system including a central processing unit (CPU) attached to and accessing system memory, and multiple computing elements. The computing elements (CEs) each include a computational core, local memory and a local direct memory access (DMA) unit. The CPU stores in the system memory multiple task queues in a one-to-one correspondence with the computing elements. Each task queue, which includes multiple task descriptors, specifies a sequence of tasks for execution by the corresponding computing element. Upon programming the computing element with task queue information of the task queue, the task descriptors of the task queue in system memory are accessed. The task descriptors of the task queue are stored in the local memory of the computing element. The accessing and the storing of the data by the CEs is performed using the local DMA unit. When the tasks of the task queue are executed by the computing element, the execution is typically performed in parallel by at least two of the computing elements. The CPU is interrupted respectively by the computing elements only upon their fully executing the tasks of their respective task queues.
    • 一种用于控制包括附接到系统存储器和访问系统存储器的中央处理单元(CPU)的系统中的并行处理流程的方法,以及多个计算元件。 计算元件(CE)各自包括计算核心,本地存储器和本地直接存储器访问(DMA)单元。 CPU与计算元件一一对应地存储系统存储器中的多个任务队列。 包括多个任务描述符的每个任务队列指定了由相应的计算元件执行的任务序列。 在使用任务队列的任务队列信息对计算单元进行编程时,访问系统存储器中任务队列的任务描述符。 任务队列的任务描述符存储在计算元素的本地存储器中。 使用本地DMA单元执行由CE访问和存储数据。 当任务队列的任务由计算元件执行时,执行通常由至少两个计算元件并行执行。 CPU只有在完全执行其各自的任务队列的任务时才被计算元件分别中断。