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1. 发明授权

US06636949B2 System for handling coherence protocol races in a scalable shared memory system based on chip multiprocessing 有权
公开(公告)号：US06636949B2
公开(公告)日：2003-10-21
申请号：US10042008
申请日：2002-01-07
申请人： Luiz A. Barroso , Kourosh Gharachorloo , Andreas Nowatzyk , Robert J. Stets , Mosur K. Ravishankar
发明人： Luiz A. Barroso , Kourosh Gharachorloo , Andreas Nowatzyk , Robert J. Stets , Mosur K. Ravishankar
IPC分类号： G06F1200
CPC分类号： G06F12/0826 , G06F12/0828 , G06F2212/621 , Y10S707/99938 , Y10S707/99952
摘要： In a chip multiprocessor system, the coherence protocol is split into two cooperating protocols implemented by different hardware modules. One protocol is responsible for cache coherence management within the chip, and is implemented by a second-level cache controller. The other protocol is responsible for cache coherence management across chip multiprocessor nodes, and is implemented by separate cache coherence protocol engines. The cache controller and the protocol engine within each node communicate and synchronize memory transactions involving multiple nodes to maintain cache coherence within and across the nodes. The present invention addresses race conditions that arise during this communication and synchronization.

2. 发明授权

US06622218B2 Cache coherence protocol engine and method for efficient processing of interleaved memory transactions in a multiprocessor system 失效
公开(公告)号：US06622218B2
公开(公告)日：2003-09-16
申请号：US10042029
申请日：2002-01-07
申请人： Kourosh Gharachorloo , Luiz A. Barroso , Mosur K. Ravishankar , Robert J. Stets
发明人： Kourosh Gharachorloo , Luiz A. Barroso , Mosur K. Ravishankar , Robert J. Stets
IPC分类号： G06F1200
CPC分类号： G06F12/0826 , G06F12/0828 , G06F2212/621
摘要： The present invention relates generally to a protocol engine for use in a multiprocessor computer system. The protocol engine, which implements a cache coherence protocol, includes a clock signal generator for generating signals denoting interleaved even clock periods and odd clock periods, a memory transaction state array for storing entries, each denoting the state of a respective memory transaction, and processing logic. The memory transactions are divided into even and odd transactions whose states are stored in distinct sets of entries in the memory transaction state array. The processing logic has interleaving circuitry for processing during even clock periods the even memory transactions and for processing during odd clock periods the odd memory transactions. Moreover, the protocol engine is configured to transition from one memory transaction to another in a minimum number of clock cycles. This design improves efficiency for processing commercial workloads, such as on-line transaction processing (OLTP) by taking certain steps in parallel.

3. 发明授权

US06748498B2 Scalable multiprocessor system and cache coherence method implementing store-conditional memory transactions while an associated directory entry is encoded as a coarse bit vector 失效
标题翻译：可扩展的多处理器系统和缓存一致性方法实现存储条件存储器事务，而相关联的目录条目被编码为粗位向量
公开(公告)号：US06748498B2
公开(公告)日：2004-06-08
申请号：US10042053
申请日：2002-01-07
申请人： Kourosh Gharachorloo , Luiz Andre Barroso , Mosur K. Ravishankar , Robert J. Stets , Daniel J. Scales
发明人： Kourosh Gharachorloo , Luiz Andre Barroso , Mosur K. Ravishankar , Robert J. Stets , Daniel J. Scales
IPC分类号： G06F1200
CPC分类号： G06F12/0826 , G06F12/0828 , G06F2212/621 , Y10S707/99952
摘要： A system including a plurality of processor nodes is configured to execute a cache coherence protocol that avoids the use of negative acknowledgments and ordering requirements on the underlying transaction-message interconnect/network, and implements store-conditional memory transactions. A store-conditional memory transaction succeeds if a directory tracking the state of a memory line of information unambiguously indicates that the requesting node is the exclusive owner of the memory line, if the directory ambiguously indicates that the requesting node is sharing the memory line and the requesting node is in fact sharing the memory line, or if the directory unambiguously indicates that the requesting node is sharing the memory line. The store-conditional memory transaction fails if the directory unambiguously indicates that the requesting node is not sharing the memory line, or if the directory ambiguously indicates that the requesting node may be sharing the memory line and the requesting node is in fact not sharing the memory line.
摘要翻译：包括多个处理器节点的系统被配置为执行高速缓存一致性协议，其避免对底层事务消息互连/网络使用否定确认和排序要求，并且实现存储条件存储器事务。如果跟踪存储器线的状态的目录明确地指示请求节点是存储器线的专有所有者，则存储条件存储器事务成功，如果目录模糊地指示请求节点正在共享存储器线，并且请求节点实际上共享内存线，或者如果目录明确地指示请求节点正在共享存储器线。如果目录明确地指示请求节点不共享存储器线路，或者如果目录模糊地指示请求节点可能共享存储器线且请求节点实际上不共享存储器，则存储条件存储器事务将失败线。

4. 发明授权

US06640287B2 Scalable multiprocessor system and cache coherence method incorporating invalid-to-dirty requests 失效
公开(公告)号：US06640287B2
公开(公告)日：2003-10-28
申请号：US10042009
申请日：2002-01-07
申请人： Kourosh Gharachorloo , Luiz Andre Barroso , Mosur Kumaraswamy Ravishankar , Robert J. Stets , Daniel J. Scales
发明人： Kourosh Gharachorloo , Luiz Andre Barroso , Mosur Kumaraswamy Ravishankar , Robert J. Stets , Daniel J. Scales
IPC分类号： G06F1200
CPC分类号： G06F12/0826 , G06F12/0828 , G06F2212/621
摘要： An invalid-to-dirty request permits a transition from an invalid memory state to a dirty state without requiring an up-to-date copy of the memory. The present invention is a system for supporting invalid-to-dirty memory transactions in an aggressive cache coherence protocol that minimizes directory entry locking. The nodes of a multiprocessor system each include a protocol engine that is configured to implement a distinct invalidation request that corresponds to an invalid-to-dirty memory transaction. If node O receives this distinct invalidation request while waiting for a response to an outstanding request for exclusive ownership, the protocol engine of node O is configured to treat the distinct invalidation request as applying to the memory line of information that is the subject of the outstanding request for exclusive ownership. Furthermore, if the node O receives a normal invalidation request, while it has an outstanding exclusive request, the invalidation request applies to a previous copy of the memory line of information held by the node N and therefore the protocol engine of node O is configured to ignore the normal invalidation request in this circumstance.

5. 发明授权

US07739694B2 Methods of factoring operating system functions, methods of converting operating systems, and related apparatus 有权
标题翻译：分解操作系统功能的方法，转换操作系统的方法以及相关设备
公开(公告)号：US07739694B2
公开(公告)日：2010-06-15
申请号：US10951306
申请日：2004-09-27
申请人： Galen C. Hunt , Gerald Cermak , Robert J. Stets
发明人： Galen C. Hunt , Gerald Cermak , Robert J. Stets
IPC分类号： G06F9/44 , G06F9/46
CPC分类号： G06F9/44521 , G06F8/71 , G06F9/44552 , G06F9/4484
摘要： Methods of factoring operating system functions into one or more groups of functions are described. Factorization permits operating systems that are not configured to support computing in an object-oriented environment to be used in an object oriented environment. This promotes distributed computing by enabling operating system resources to be instantiated and used across process and machine boundaries. In one embodiment, criteria are defined that govern how functions of an operating system are to be factored into one or more groups. Based on the defined criteria, the functions are factors into groups and groups of functions are when associated with programming objects that have data and methods, wherein the methods correspond to the operating system functions. Applications can call methods on the programming objects either directly or indirectly that, in turn, call operating system functions.
摘要翻译：描述将操作系统功能分解为一组或多组功能的方法。因式分解允许未配置为支持面向对象环境中的计算的操作系统，以在面向对象的环境中使用。这通过使操作系统资源在过程和机器边界之间实例化和使用来促进分布式计算。在一个实施例中，定义了规范操作系统的功能如何被考虑到一个或多个组中的标准。基于定义的标准，功能是组与组的功能，当与具有数据和方法的编程对象相关联时，其中该方法对应于操作系统功能。应用程序可以直接或间接调用编程对象的方法，从而调用操作系统功能。

6. 发明授权

US08452656B2 Prioritizing ad review, by using expected revenue for example, in an advertising system 有权
标题翻译：通过使用广告系统中的预期收入来确定广告评估的优先级
公开(公告)号：US08452656B2
公开(公告)日：2013-05-28
申请号：US11170727
申请日：2005-06-29
申请人： Dipchand Nishar , Robert J. Stets
发明人： Dipchand Nishar , Robert J. Stets
IPC分类号： G06F17/00
CPC分类号： G06Q30/02 , G06Q30/0247
摘要： Ads are reviewed manually once they have reached a certain expected revenue threshold (instead of attempting to review manually all incoming ads as was done in the past). This review process considers the fact that the many advertisers submit hundreds or even thousands of ads with each individually returning relatively little revenue. Such a review process should greatly reduce the number of ads, or at least to prioritize the order of ads, pending manual approval. The threshold may be set to the approximate cost of manually approving an ad, thereby reducing ad reviews pending manual review significantly. A classification of the ad (e.g., forbidden, suspicious, unchecked, an ad category, etc.), which may be determined by automated means for example, may also be used when prioritizing the order of ads pending manual approval. Revenue-based scores may also be used to control a review of an advertisement. For example, such scores may be used to select one of a plurality of review protocols.
摘要翻译：一旦达到一定的预期收入限制，广告就会手动进行审核（而不是像以前一样手动查看所有收到的广告）。这个审查过程认为，许多广告客户提交数百甚至数千个广告，每个广告各自收回的收入相对较少。这样的审查过程应大大减少广告的数量，或者至少将广告的顺序放在首位，等待手动审批。阈值可以设置为手动批准广告的大概成本，从而大大降低了待审核的广告评论。当优先处理待批准的广告顺序时，也可以使用例如可以通过自动化手段确定的广告的分类（例如，禁止，可疑，未经检查，广告类别等）。基于收入的分数也可用于控制广告的审查。例如，这样的分数可以用于选择多个评论协议之一。

7. 发明授权

US08788336B1 Estimating cost and/or performance information for an advertisement in an advertising system 有权
标题翻译：估计广告系统中广告的成本和/或性能信息
公开(公告)号：US08788336B1
公开(公告)日：2014-07-22
申请号：US10749115
申请日：2003-12-30
申请人： Arash Baratloo , Monika H. Henzinger , Ming-Yee Iu , Wilburt Labio , Zhe Qian , Keith Randall , Robert J. Stets
发明人： Arash Baratloo , Monika H. Henzinger , Ming-Yee Iu , Wilburt Labio , Zhe Qian , Keith Randall , Robert J. Stets
IPC分类号： G06Q30/00
CPC分类号： G06Q30/08 , G06Q30/0242
摘要： An advertiser may be provided with fast and accurate estimates of the future cost and/or performance information for one or more actual or hypothetical ads (generally referred to as “proto-ads”). Past auction information may be used to simulate auctions that the proto-ad would have competed in. The proto-ad may then participate in a “replay” of such past auctions.
摘要翻译：可以向广告客户提供对于一个或多个实际或假设广告（通常称为“原型广告”）的未来成本和/或性能信息的快速和准确估计。过去的拍卖信息可能被用于模拟原型广告竞争的拍卖。然后，原创广告可以参与过去拍卖的“重播”。

8. 发明授权

US08423413B2 Advertisement approval 有权
标题翻译：广告批准
公开(公告)号：US08423413B2
公开(公告)日：2013-04-16
申请号：US11026415
申请日：2004-12-30
申请人： Gregory Joseph Badros , Robert J. Stets , Lucy Zhang
发明人： Gregory Joseph Badros , Robert J. Stets , Lucy Zhang
IPC分类号： G06Q30/00
CPC分类号： G06Q30/02 , G06Q30/0269
摘要： An advertisement for use with an online ad serving system may be automatically checked for compliance with one or more policies of the online ad serving system. If the advertisement is approved, then it is allowed by be served by the ad serving system. Follow up checks of the advertisement may be scheduled. One follow up check may be to test a landing page of the advertisement for compliance with policies. If the advertisement is not approved, hints for making the ad comply with one or more violated policies may be provided to an advertiser associated with the ad, and/or an ad serving system customer service representative. Determining whether or not to approve the advertisement may include determining violations of one or more policies by the advertisement, and, for each of the violations, determining whether or not to exempt the violation.
摘要翻译：可以自动检查与在线广告投放系统一起使用的广告是否符合在线广告投放系统的一个或多个策略。如果广告被批准，则允许由广告投放系统提供。广告的后续检查可能会安排。一个后续检查可能是测试广告的着陆页是否符合政策。如果广告未被批准，则可以向与广告相关联的广告客户和/或广告服务系统客户服务代表提供使广告符合一个或多个违反的策略的提示。确定是否批准广告可以包括确定广告的一个或多个策略的违规，以及针对每个违规，确定是否豁免违规。

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