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1. 发明授权

US08502287B2 Semiconductor devices with enclosed void cavities 有权
标题翻译：具有封闭空隙的半导体器件
公开(公告)号：US08502287B2
公开(公告)日：2013-08-06
申请号：US12902805
申请日：2010-10-12
申请人： Ljubo Radic , Edouard D. de Frésart
发明人： Ljubo Radic , Edouard D. de Frésart
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/42368 , H01L29/42376 , H01L29/66734 , H01L2924/0002 , H01L2924/00
摘要： Field effect devices and ICs with very low gate-drain capacitance Cgd are provided by forming a substantially empty void between the gate and the drain regions. For vertical FETS a cavity is etched in the semiconductor (SC) and provided with a gate dielectric liner. A poly-SC gate deposited in the cavity has a central fissure (empty pipe) extending through to the underlying SC. This fissure is used to etch the void in the SC beneath the poly-gate. The fissure is then closed by a dielectric plug formed by deposition or oxidation without significantly filling the etched void. Conventional process steps are used to provide the source and body regions around the cavity containing the gate, and to provide a drift space and drain region below the body region. The etched void between the gate and drain provides lower Cgd and Ron*Qg than can be achieved using low k dielectrics.
摘要翻译：通过在栅极和漏极区域之间形成基本上空的空隙来提供具有非常低栅极 - 漏极电容Cgd的场效应器件和IC。对于垂直FETS，在半导体（SC）中蚀刻空腔并且设置有栅极电介质衬垫。沉积在空腔中的多晶硅栅极具有延伸到下面的SC的中心裂隙（空管）。这种裂缝用于蚀刻多晶硅下面的SC中的空隙。然后通过由沉积或氧化形成的介电塞而封闭裂缝，而不会明显地填充蚀刻的空隙。常规的工艺步骤用于在包含栅极的空腔周围提供源区和体区，并在体区下面提供漂移空间和漏区。栅极和漏极之间的蚀刻空隙提供比使用低k电介质可以实现的更低的Cgd和Ron * Qg。

2. 发明申请

US20100084705A1 SEMICONDUCTOR DEVICES HAVING REDUCED GATE-DRAIN CAPACITANCE AND METHODS FOR THE FABRICATION THEREOF 有权
标题翻译：具有降低的排气容量的半导体器件及其制造方法
公开(公告)号：US20100084705A1
公开(公告)日：2010-04-08
申请号：US12627739
申请日：2009-11-30
申请人： Ljubo Radic , Edouard D. de Frésart
发明人： Ljubo Radic , Edouard D. de Frésart
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/42368 , H01L29/42376 , H01L29/66734
摘要： Embodiments of a method for fabricating a semiconductor device having a reduced gate-drain capacitance are provided. In one embodiment, the method includes the steps of etching a trench in a semiconductor substrate utilizing an etch mask, widening the trench to define overhanging regions of the etch mask extending partially over the trench, and depositing a gate electrode material into the trench and onto the overhanging regions. The gate electrode material merges between the overhanging regions prior to the filling of the trench to create an empty fissure within the trench. A portion of the semiconductor substrate is removed through the empty fissure to form a void cavity proximate the trench.
摘要翻译：提供了具有减小的栅极 - 漏极电容的半导体器件的制造方法的实施例。在一个实施例中，该方法包括以下步骤：利用蚀刻掩模蚀刻半导体衬底中的沟槽，加宽沟槽以限定部分地延伸到沟槽上的蚀刻掩模的悬垂区域，以及将栅电极材料沉积到沟槽中突出地区。栅极电极材料在填充沟槽之前在悬垂区域之间合并，以在沟槽内产生空隙。半导体衬底的一部分通过空隙去除以在沟槽附近形成空隙。

3. 发明授权

US07919388B2 Methods for fabricating semiconductor devices having reduced gate-drain capacitance 有权
标题翻译：制造具有降低的栅 - 漏电容的半导体器件的方法
公开(公告)号：US07919388B2
公开(公告)日：2011-04-05
申请号：US12627739
申请日：2009-11-30
申请人： Ljubo Radic , Edouard D. de Frésart
发明人： Ljubo Radic , Edouard D. de Frésart
IPC分类号： H01L29/72
CPC分类号： H01L29/7813 , H01L29/42368 , H01L29/42376 , H01L29/66734
摘要： Embodiments of a method for fabricating a semiconductor device having a reduced gate-drain capacitance are provided. In one embodiment, the method includes the steps of etching a trench in a semiconductor substrate utilizing an etch mask, widening the trench to define overhanging regions of the etch mask extending partially over the trench, and depositing a gate electrode material into the trench and onto the overhanging regions. The gate electrode material merges between the overhanging regions prior to the filling of the trench to create an empty fissure within the trench. A portion of the semiconductor substrate is removed through the empty fissure to form a void cavity proximate the trench.
摘要翻译：提供了具有减小的栅极 - 漏极电容的半导体器件的制造方法的实施例。在一个实施例中，该方法包括以下步骤：利用蚀刻掩模蚀刻半导体衬底中的沟槽，加宽沟槽以限定部分地延伸到沟槽上的蚀刻掩模的悬垂区域，以及将栅电极材料沉积到沟槽中突出地区。栅极电极材料在填充沟槽之前在悬垂区域之间合并，以在沟槽内产生空隙。半导体衬底的一部分通过空隙去除以在沟槽附近形成空隙。

4. 发明授权

US08735978B2 Semiconductor devices having reduced gate-drain capacitance 有权
标题翻译：具有降低的栅 - 漏电容的半导体器件
公开(公告)号：US08735978B2
公开(公告)日：2014-05-27
申请号：US13034084
申请日：2011-02-24
申请人： Ljubo Radic , Edouard D. de Frésart
发明人： Ljubo Radic , Edouard D. de Frésart
IPC分类号： H01L29/72
CPC分类号： H01L29/7813 , H01L29/42368 , H01L29/42376 , H01L29/66734
摘要： Embodiments of a semiconductor device include a semiconductor substrate having a first surface and a second surface opposed to the first surface, a trench formed in the semiconductor substrate and extending from the first surface partially through the semiconductor substrate, a gate electrode material deposited in the trench, and a void cavity in the semiconductor substrate between the gate electrode material and the second surface. A portion of the semiconductor substrate is located between the void cavity and the second surface.
摘要翻译：半导体器件的实施例包括具有第一表面和与第一表面相对的第二表面的半导体衬底，形成在半导体衬底中并且从第一表面部分延伸穿过半导体衬底的沟槽，沉积在沟槽中的栅电极材料，以及在栅电极材料和第二表面之间的半导体衬底中的空隙。半导体衬底的一部分位于空腔和第二表面之间。

5. 发明申请

US20110147835A1 SEMICONDUCTOR DEVICES HAVING REDUCED GATE-DRAIN CAPACITANCE 有权
标题翻译：具有降低排气电容的半导体器件
公开(公告)号：US20110147835A1
公开(公告)日：2011-06-23
申请号：US13034084
申请日：2011-02-24
申请人： Ljubo Radic , Edouard D. de Frésart
发明人： Ljubo Radic , Edouard D. de Frésart
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/42368 , H01L29/42376 , H01L29/66734
摘要： Embodiments of a semiconductor device include a semiconductor substrate having a first surface and a second surface opposed to the first surface, a trench formed in the semiconductor substrate and extending from the first surface partially through the semiconductor substrate, a gate electrode material deposited in the trench, and a void cavity in the semiconductor substrate between the gate electrode material and the second surface. A portion of the semiconductor substrate is located between the void cavity and the second surface.
摘要翻译：半导体器件的实施例包括具有第一表面和与第一表面相对的第二表面的半导体衬底，形成在半导体衬底中并且从第一表面部分延伸穿过半导体衬底的沟槽，沉积在沟槽中的栅电极材料，以及在栅电极材料和第二表面之间的半导体衬底中的空隙。半导体衬底的一部分位于空腔和第二表面之间。

6. 发明申请

US20110024806A1 SEMICONDUCTOR DEVICES WITH ENCLOSED VOID CAVITIES 有权
标题翻译：具有封闭空穴的半导体器件
公开(公告)号：US20110024806A1
公开(公告)日：2011-02-03
申请号：US12902805
申请日：2010-10-12
申请人： Ljubo Radic , Edouard D. de Frésart
发明人： Ljubo Radic , Edouard D. de Frésart
IPC分类号： H01L29/78 , H01L23/522
CPC分类号： H01L29/7813 , H01L29/42368 , H01L29/42376 , H01L29/66734 , H01L2924/0002 , H01L2924/00
摘要： Field effect devices and ICs with very low gate-drain capacitance Cgd are provided by forming a substantially empty void between the gate and the drain regions. For vertical FETS a cavity is etched in the semiconductor (SC) and provided with a gate dielectric liner. A poly-SC gate deposited in the cavity has a central fissure (empty pipe) extending through to the underlying SC. This fissure is used to etch the void in the SC beneath the poly-gate. The fissure is then closed by a dielectric plug formed by deposition or oxidation without significantly filling the etched void. Conventional process steps are used to provide the source and body regions around the cavity containing the gate, and to provide a drift space and drain region below the body region. The etched void between the gate and drain provides lower Cgd and Ron*Qg than can be achieved using low k dielectrics.
摘要翻译：通过在栅极和漏极区域之间形成基本上空的空隙来提供具有非常低栅极 - 漏极电容Cgd的场效应器件和IC。对于垂直FETS，在半导体（SC）中蚀刻空腔并且设置有栅极电介质衬垫。沉积在空腔中的多晶硅栅极具有延伸到下面的SC的中心裂隙（空管）。这种裂缝用于蚀刻多晶硅下面的SC中的空隙。然后通过由沉积或氧化形成的介电塞而封闭裂缝，而不会明显地填充蚀刻的空隙。常规的工艺步骤用于在包含栅极的空腔周围提供源区和体区，并在体区下面提供漂移空间和漏区。栅极和漏极之间的蚀刻空隙提供比使用低k电介质可以实现的更低的Cgd和Ron * Qg。

7. 发明授权

US07510938B2 Semiconductor superjunction structure 有权
标题翻译：半导体超结构结构
公开(公告)号：US07510938B2
公开(公告)日：2009-03-31
申请号：US11510030
申请日：2006-08-25
申请人： Edouard D. de Frésart
发明人： Edouard D. de Frésart
IPC分类号： H01L21/336
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/165 , H01L29/205 , H01L29/267 , H01L29/66712 , H01L29/73 , H01L29/772 , H01L29/7848 , H01L29/861 , Y10S438/912
摘要： Semiconductor structures and methods are provided for a semiconductor device (54-11, 54-12) employing a superjunction structure (81). The method comprises, forming (52-6) first spaced-apart regions (70-1, 70-2, 70-3, 70-4, etc.) of a first semiconductor material (70) of a first conductivity type, forming (52-9) second spaced-apart regions (74-1, 74-2, 74-3, etc.) of a second semiconductor material (74) of opposite conductivity type interleaved with the first space-apart regions (70-1, 70-2, 70-3, 70-4, etc.) with PN junctions therebetween, thereby forming a superjunction structure, wherein the second regions have higher mobility than the first regions for the same carrier type. Other regions (88) are provided in contact with the superjunction structure (81) to direct control current flow therethrough. In a preferred embodiment, the first material (70) is relaxed SiGe and the second material (74) is strained silicon.
摘要翻译：半导体结构和方法被提供用于采用超结构结构（81）的半导体器件（54-11,54-12）。该方法包括：形成（52-6）第一导电类型的第一半导体材料（70）的第一间隔开的区域（70-1,70-2,70-3,70-4等），形成（52-9）与第一空间分开区域（70-1）交错的相反导电类型的第二半导体材料（74）的第二间隔开的区域（74-1,74-2,74-3等），70-2,70-3,70-4等），其间具有PN结，从而形成超结构结构，其中第二区具有比相同载流子类型的第一区更高的迁移率。提供与超结构结构（81）接触的其它区域（88）以引导其中的控制电流流动。在优选实施例中，第一材料（70）是松弛的SiGe，第二材料（74）是应变硅。

8. 发明申请

US20090286372A1 SUPERJUNCTION TRENCH DEVICE FORMATION METHODS 有权
标题翻译：超音速装置形成方法
公开(公告)号：US20090286372A1
公开(公告)日：2009-11-19
申请号：US12511849
申请日：2009-07-29
申请人： Edouard D. de Frésart , Robert W. Baird
发明人： Edouard D. de Frésart , Robert W. Baird
IPC分类号： H01L21/336 , H01L21/20
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/1054 , H01L29/165 , H01L29/42368 , H01L29/66734
摘要： Methods for forming semiconductor structures are provided for a semiconductor device employing a superjunction structure and overlying trench with embedded control gate. An embodiment comprises forming interleaved first and second spaced-apart regions of first and second semiconductor materials of different conductivity type and different mobilities so that the second semiconductor material has a higher mobility for the same carrier type than the first semiconductor material, and providing an overlying third semiconductor material in which a trench is formed with sidewalls having thereon a fourth semiconductor material that has a higher mobility than the third material, adapted to carry current between source regions, through the fourth semiconductor material in the trench and the second semiconductor material in the device drift space to the drain. In a further embodiment, the first and third semiconductor materials are relaxed materials and the second and fourth semiconductor materials are strained semiconductor materials.
摘要翻译：为半导体器件提供了形成半导体结构的方法，该半导体器件采用超结构结构和具有嵌入式控制栅极的上覆沟槽。一个实施例包括形成具有不同导电类型和不同迁移率的第一和第二半导体材料的交错的第一和第二间隔开的区域，使得第二半导体材料对于与第一半导体材料相同的载体类型具有较高的迁移率，并提供覆盖第三半导体材料，其中沟槽形成有侧壁，其上具有第四半导体材料，第四半导体材料具有比第三材料更高的迁移率，适于在源极区域之间通过沟槽中的第四半导体材料和第二半导体材料中的第二半导体材料器件漂移空间到漏极。在另一个实施例中，第一和第三半导体材料是松弛材料，第二和第四半导体材料是应变半导体材料。

9. 发明授权

US07592230B2 Trench power device and method 有权
标题翻译：沟槽动力装置及方法
公开(公告)号：US07592230B2
公开(公告)日：2009-09-22
申请号：US11510552
申请日：2006-08-25
申请人： Edouard D. de Frésart , Robert W. Baird
发明人： Edouard D. de Frésart , Robert W. Baird
IPC分类号： H01L21/336
CPC分类号： H01L29/66348 , H01L29/73 , H01L29/7397
摘要： Means and methods are provided for trench TMOS devices (41-10, 11, 12), comprising, providing a first semiconductor (53, 53′) of a first composition having an upper surface (541), with a body portion (54) proximate the upper surface (541), a drift portion (46, 83) spaced apart from the upper surface (541) and a trench (49, 49′) having sidewalls (493) extending from the upper surface (541) into the drift portion (46, 83). A second semiconductor (56) adapted to provide a higher mobility layer is applied on the trench sidewalls (493) where parts (78) of the body portion (54) are exposed. A dielectric (70) covers the higher mobility layer (56) and separates it from a control gate (72) in the trench (49, 49′). Source regions (68) formed in the body portion (54) proximate the upper surface (491) communicate with the higher mobility layer (56). When biased, source-drain current (87, 87′) flows from the source regions (68) through gate induced channels (78) in the higher mobility layer (56) and into the drift portion (46, 83) where it is extracted by a drain (42) or other connection coupled to the drift portion (46, 83).
摘要翻译：提供了用于沟槽TMOS器件（41-10,11,12）的方法和方法，包括：提供具有上表面（541）的第一组合物的第一半导体（53,53'）与主体部分（54）邻近上表面（541），与上表面（541）间隔开的漂移部分（46,83）和具有从上表面（541）延伸到漂移体（491）中的侧壁（493）的沟槽部分（46,83）。适于提供更高迁移率层的第二半导体（56）被施加在主体部分（54）的部分（78）暴露的沟槽侧壁（493）上。电介质（70）覆盖高迁移率层（56）并将其与沟槽（49,49'）中的控制栅极（72）分离。形成在靠近上表面（491）的主体部分（54）中的源区（68）与较高迁移率层（56）连通。当偏置时，源极 - 漏极电流（87,87'）从源极区（68）流过高迁移率层（56）中的栅极感应通道（78）并流入其中被提取的漂移部分（46,83）通过连接到漂移部分（46,83）的排水（42）或其它连接。

10. 发明申请

US20080048175A1 Semiconductor superjunction structure 有权
标题翻译：半导体超结构结构
公开(公告)号：US20080048175A1
公开(公告)日：2008-02-28
申请号：US11510030
申请日：2006-08-25
申请人： Edouard D. de Frésart
发明人： Edouard D. de Frésart
IPC分类号： H01L31/00
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/165 , H01L29/205 , H01L29/267 , H01L29/66712 , H01L29/73 , H01L29/772 , H01L29/7848 , H01L29/861 , Y10S438/912
摘要： Semiconductor structures and methods are provided for a semiconductor device (54-11, 54-12) employing a superjunction structure (81). The method comprises, forming (52-6) first spaced-apart regions (70-1, 70-2, 70-3, 70-4, etc.) of a first semiconductor material (70) of a first conductivity type, forming (52-9) second spaced-apart regions (74-1, 74-2, 74-3, etc.) of a second semiconductor material (74) of opposite conductivity type interleaved with the first space-apart regions (70-1, 70-2, 70-3, 70-4, etc.) with PN junctions therebetween, thereby forming a superjunction structure, wherein the second regions have higher mobility than the first regions for the same carrier type. Other regions (88) are provided in contact with the superjunction structure (81) to direct control current flow therethrough. In a preferred embodiment, the first material (70) is relaxed SiGe and the second material (74) is strained silicon.
摘要翻译：半导体结构和方法被提供用于采用超结构结构（81）的半导体器件（54-11,54-12）。该方法包括：形成第一导电类型的第一半导体材料（70）的第一间隔开的第一间隔开的区域（70-1,70-2,73-3,70-4等），形成（52-9）与第一间隔开区域（70-1）交错的相反导电类型的第二半导体材料（74）的第二间隔区域（74-1,74-2,74-3等），70-2,70-3,30-4等），其间具有PN结，从而形成超结构结构，其中第二区具有比相同载流子类型的第一区更高的迁移率。提供与超结构结构（81）接触的其它区域（88）以引导其中的控制电流流动。在优选实施例中，第一材料（70）是松弛的SiGe，第二材料（74）是应变硅。

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