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1. 发明授权

US08390024B2 Electrostatic discharge (ESD) protection circuit 有权
标题翻译：静电放电（ESD）保护电路
公开(公告)号：US08390024B2
公开(公告)日：2013-03-05
申请号：US12757612
申请日：2010-04-09
申请人： Liping Ren , Hsiao-Chin Tuan , Dah-Chuen Ho
发明人： Liping Ren , Hsiao-Chin Tuan , Dah-Chuen Ho
IPC分类号： H01L27/06
CPC分类号： H01L27/0259 , H01L2224/16225 , H01L2924/1301 , H01L2924/13034 , H01L2924/1305 , H01L2924/13091 , H01L2924/00 , H01L2924/00014
摘要： An electrostatic discharge (ESD) protection circuit includes at least one bipolar transistor. At least one isolation structure is disposed in a substrate. The at least one isolation structure is configured to electrically isolate two terminals of the at least one bipolar transistor. At least one diode is electrically coupled with the at least one bipolar transistor, wherein a junction interface of the at least one diode is disposed adjacent the at least one isolation structure.
摘要翻译：静电放电（ESD）保护电路包括至少一个双极晶体管。在衬底中设置至少一个隔离结构。所述至少一个隔离结构被配置为电隔离所述至少一个双极晶体管的两个端子。至少一个二极管与所述至少一个双极晶体管电耦合，其中所述至少一个二极管的结界面邻近所述至少一个隔离结构设置。

2. 发明授权

US08691100B2 Concave and convex micromirrors and methods of making the same 有权
标题翻译：凹凸微镜及其制作方法
公开(公告)号：US08691100B2
公开(公告)日：2014-04-08
申请号：US11450236
申请日：2006-06-09
申请人： Dah-Chuen Ho , Eugene Chu , Yuh-Haw Chang , Fei-Yun Chen , Michael Wu , Eric Chao
发明人： Dah-Chuen Ho , Eugene Chu , Yuh-Haw Chang , Fei-Yun Chen , Michael Wu , Eric Chao
IPC分类号： B29D11/00 , G02B26/00
CPC分类号： G02B26/0833 , G02B26/0841
摘要： A method comprising providing a first substrate and forming a first sacrificial layer over the first substrate, the first sacrificial layer comprising a curved surface portion, and forming a curved micromirror by depositing a reflective material over at the curved surface portion.
摘要翻译：一种方法，包括提供第一衬底并在所述第一衬底上形成第一牺牲层，所述第一牺牲层包括弯曲表面部分，以及通过在所述弯曲表面部分上沉积反射材料形成弯曲微镜。

3. 发明授权

US07608889B2 Lateral diffusion metal-oxide-semiconductor structure 有权
标题翻译：侧向扩散金属氧化物半导体结构
公开(公告)号：US07608889B2
公开(公告)日：2009-10-27
申请号：US11864278
申请日：2007-09-28
申请人： Dah-Chuen Ho , Chien-Shao Tang , Zhe-Yi Wang , Yu-Chang Jong
发明人： Dah-Chuen Ho , Chien-Shao Tang , Zhe-Yi Wang , Yu-Chang Jong
IPC分类号： H01L29/78
CPC分类号： H01L29/7835 , H01L29/0653 , H01L29/4933 , H01L29/66659
摘要： A lateral diffusion metal-oxide-semiconductor (LDMOS) structure comprises a gate, a source, a drain and a shallow trench isolation. The shallow trench isolation is formed between the drain and the gate to withstand high voltages, applied to the drain, and is associated with the semiconductor substrate to form a recess. As such, the surface of the shallow trench isolation is lower than the surface of the semiconductor substrate. Optionally, the surface of the shallow trench isolation is lower than the surface of the semiconductor substrate by 300-1500 angstroms.
摘要翻译：横向扩散金属氧化物半导体（LDMOS）结构包括栅极，源极，漏极和浅沟槽隔离。浅沟槽隔离形成在漏极和栅极之间以承受施加到漏极上的高电压，并且与半导体衬底相关联以形成凹部。因此，浅沟槽隔离的表面低于半导体衬底的表面。可选地，浅沟槽隔离的表面比半导体衬底的表面低300-1500埃。

4. 发明申请

US20060110842A1 Method and apparatus for preventing metal/silicon spiking in MEMS devices 审中-公开
标题翻译：用于防止MEMS器件中金属/硅尖峰的方法和装置
公开(公告)号：US20060110842A1
公开(公告)日：2006-05-25
申请号：US10996234
申请日：2004-11-23
申请人： Yuh-Hwa Chang , Fei-Yun Chen , Jiann-Tyng Tzeng , Cheng-Yu Chu , Chun-Kai Peng , Chih-Chieh Yeh , Chih-Heng Po , Dah-Chuen Ho
发明人： Yuh-Hwa Chang , Fei-Yun Chen , Jiann-Tyng Tzeng , Cheng-Yu Chu , Chun-Kai Peng , Chih-Chieh Yeh , Chih-Heng Po , Dah-Chuen Ho
IPC分类号： H01L21/00 , H01L31/0203
CPC分类号： B81C1/00253 , B81C2201/0178 , B81C2201/053
摘要： The disclosure relates to a method and apparatus for preventing extrusion or spiking of a metal atom from a metallization layer to other layers of a silicon wafer. In one embodiment, the method includes forming a silicon-on-ship device with a MEMS component on the substrate. The MEMS component may include one or more metal or metallic alloys. To prevent spiking from the MEMS component, the sides thereof can be coated with one ore more spacer or barrier layers. In one embodiment, oxygen plasma and thermal oxidation methods are used to deposit spacers. In another embodiment, an oxide layer is deposited over the wafer, covering the substrate and the MEMS component. Selective etching or anisotropic etching can be used to remove the oxide layer from certain regions of the MEMS and the substrate while covering the sidewalls. An amorphous silicon layer can then be deposited to cover the MEMS device.
摘要翻译：本公开涉及一种用于防止金属原子从金属化层挤出或尖峰到硅晶片其它层的方法和装置。在一个实施例中，该方法包括在衬底上形成具有MEMS部件的在船上的硅装置。 MEMS组件可以包括一种或多种金属或金属合金。为了防止从MEMS部件尖尖，其侧面可以涂覆一个或多个间隔物或阻挡层。在一个实施例中，使用氧等离子体和热氧化方法来沉积间隔物。在另一个实施例中，氧化物层沉积在晶片上，覆盖衬底和MEMS部件。可以使用选择性蚀刻或各向异性蚀刻从覆盖侧壁的MEMS和衬底的某些区域去除氧化物层。然后可以沉积非晶硅层以覆盖MEMS器件。

5. 发明授权

US08324705B2 Schottky diodes having low-voltage and high-concentration rings 有权
标题翻译：具有低电压和高浓度环的肖特基二极管
公开(公告)号：US08324705B2
公开(公告)日：2012-12-04
申请号：US12127629
申请日：2008-05-27
申请人： Chien-Shao Tang , Dah-Chuen Ho , Yu-Chang Jong , Zhe-Yi Wang , Yuh-Hwa Chang , Yogendra Yadav
发明人： Chien-Shao Tang , Dah-Chuen Ho , Yu-Chang Jong , Zhe-Yi Wang , Yuh-Hwa Chang , Yogendra Yadav
IPC分类号： H01L29/872
CPC分类号： H01L27/0629 , H01L29/0619 , H01L29/0649 , H01L29/872
摘要： An integrated circuit structure includes a semiconductor substrate; a first well region of a first conductivity type over the semiconductor substrate; a second well region of a second conductivity type opposite the first conductivity type encircling the first well region; and a metal-containing layer over and adjoining the first well region and extending over at least an inner portion of the second well region. The metal-containing layer and the first well region form a Schottky barrier. The integrated circuit structure further includes an isolation region encircling the metal-containing layer; and a third well region of the second conductivity type encircling at least a central portion of the first well region. The third well region has a higher impurity concentration than the second well region, and includes a top surface adjoining the metal-containing layer, and a bottom surface higher than bottom surfaces of the first and the second well regions.
摘要翻译：集成电路结构包括半导体衬底; 半导体衬底上的第一导电类型的第一阱区; 与第一导电类型相反的第二导电类型的环绕第一阱区的第二阱区; 以及在所述第一阱区上并邻接所述第一阱区并且在所述第二阱区的至少内部部分上延伸的含金属层。含金属层和第一阱区形成肖特基势垒。所述集成电路结构还包括环绕所述含金属层的隔离区域; 以及第二导电类型的第三阱区域，其环绕至少第一阱区域的中心部分。第三阱区域具有比第二阱区域更高的杂质浓度，并且包括邻近含金属层的顶表面和高于第一阱区域和第二阱区域的底表面的底表面。

6. 发明申请

US20090294865A1 Schottky Diodes Having Low-Voltage and High-Concentration Rings 有权
标题翻译：具有低电压和高浓度环的肖特基二极管
公开(公告)号：US20090294865A1
公开(公告)日：2009-12-03
申请号：US12127629
申请日：2008-05-27
申请人： Chien-Shao Tang , Dah-Chuen Ho , Yu-Chang Jong , Zhe-Yi Wang , Yuh-Hwa Chang , Yogendra Yadav
发明人： Chien-Shao Tang , Dah-Chuen Ho , Yu-Chang Jong , Zhe-Yi Wang , Yuh-Hwa Chang , Yogendra Yadav
IPC分类号： H01L27/06
CPC分类号： H01L27/0629 , H01L29/0619 , H01L29/0649 , H01L29/872
摘要： An integrated circuit structure includes a semiconductor substrate; a first well region of a first conductivity type over the semiconductor substrate; a second well region of a second conductivity type opposite the first conductivity type encircling the first well region; and a metal-containing layer over and adjoining the first well region and extending over at least an inner portion of the second well region. The metal-containing layer and the first well region form a Schottky barrier. The integrated circuit structure further includes an isolation region encircling the metal-containing layer; and a third well region of the second conductivity type encircling at least a central portion of the first well region. The third well region has a higher impurity concentration than the second well region, and includes a top surface adjoining the metal-containing layer, and a bottom surface higher than bottom surfaces of the first and the second well regions.
摘要翻译：集成电路结构包括半导体衬底; 半导体衬底上的第一导电类型的第一阱区; 与第一导电类型相反的第二导电类型的环绕第一阱区的第二阱区; 以及在所述第一阱区上并邻接所述第一阱区并且在所述第二阱区的至少内部部分上延伸的含金属层。含金属层和第一阱区形成肖特基势垒。所述集成电路结构还包括环绕所述含金属层的隔离区域; 以及第二导电类型的第三阱区域，其环绕至少第一阱区域的中心部分。第三阱区域具有比第二阱区域更高的杂质浓度，并且包括邻近含金属层的顶表面和高于第一阱区域和第二阱区域的底表面的底表面。

7. 发明申请

US20070063250A1 Split gate field effect transistor device with aligned gate electrode sidewalls 审中-公开
标题翻译：分离栅场效应晶体管器件具有对准的栅电极侧壁
公开(公告)号：US20070063250A1
公开(公告)日：2007-03-22
申请号：US11230348
申请日：2005-09-20
申请人： Haw-Chuan Wu , Wong-Chu Chu , Dah-Chuen Ho , Kuang Yang
发明人： Haw-Chuan Wu , Wong-Chu Chu , Dah-Chuen Ho , Kuang Yang
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11521
摘要： A split gate field effect transistor is fabricated with a sidewall of a control gate electrode aligned with a sidewall of a floating gate electrode. The aligned sidewalls are on a side of the split gate field effect transistor device opposite the control gate electrode channel of the split gate field effect transistor device. The aligned sidewalls provide for enhanced performance of the split gate field effect transistor device.
摘要翻译：制造分离栅场效应晶体管，其中控制栅电极的侧壁与浮栅电极的侧壁对准。对齐的侧壁位于分裂栅极场效应晶体管器件的与分离栅极场效应晶体管器件的控制栅极通道相对的一侧。对齐的侧壁提供了分裂栅极场效应晶体管器件的增强的性能。

8. 发明授权

US07808069B2 Robust structure for HVPW Schottky diode 有权
标题翻译： HVPW肖特基二极管的稳健结构
公开(公告)号：US07808069B2
公开(公告)日：2010-10-05
申请号：US12347478
申请日：2008-12-31
申请人： Dah-Chuen Ho , Chien-Shao Tang , Yu-Chang Jong , Zhe-Yi Wang
发明人： Dah-Chuen Ho , Chien-Shao Tang , Yu-Chang Jong , Zhe-Yi Wang
IPC分类号： H01L27/095
CPC分类号： H01L29/872 , H01L29/0619
摘要： A high-voltage Schottky diode including a deep P-well having a first width is formed on the semiconductor substrate. A doped P-well is disposed over the deep P-well and has a second width that is less than the width of the deep P-well. An M-type guard ring is formed around the upper surface of the second doped well, A Schottky metal is disposed on an upper surface of the second doped well and the N-type guard ring.
摘要翻译：包括具有第一宽度的深P阱的高电压肖特基二极管形成在半导体衬底上。掺杂的P阱设置在深P阱上，并且具有小于深P阱的宽度的第二宽度。在第二掺杂阱的上表面周围形成M型保护环，肖特基金属设置在第二掺杂阱的上表面和N型保护环上。

9. 发明申请

US20090085112A1 LATERAL DIFFUSION METAL-OXIDE-SEMICONDUCTOR STRUCTURE 有权
标题翻译：侧向扩散金属氧化物半导体结构
公开(公告)号：US20090085112A1
公开(公告)日：2009-04-02
申请号：US11864278
申请日：2007-09-28
申请人： Dah-Chuen Ho , Chien-Shao Tang , Zhe-Yi Wang , Yu-Chang Jong
发明人： Dah-Chuen Ho , Chien-Shao Tang , Zhe-Yi Wang , Yu-Chang Jong
IPC分类号： H01L29/78
CPC分类号： H01L29/7835 , H01L29/0653 , H01L29/4933 , H01L29/66659
摘要： A lateral diffusion metal-oxide-semiconductor (LDMOS) structure comprises a gate, a source, a drain and a shallow trench isolation. The shallow trench isolation is formed between the drain and the gate to withstand high voltages, applied to the drain, and is associated with the semiconductor substrate to form a recess. As such, the surface of the shallow trench isolation is lower than the surface of the semiconductor substrate. Optionally, the surface of the shallow trench isolation is lower than the surface of the semiconductor substrate by 300-1500 angstroms.
摘要翻译：横向扩散金属氧化物半导体（LDMOS）结构包括栅极，源极，漏极和浅沟槽隔离。浅沟槽隔离形成在漏极和栅极之间以承受施加到漏极上的高电压，并且与半导体衬底相关联以形成凹部。因此，浅沟槽隔离的表面低于半导体衬底的表面。可选地，浅沟槽隔离的表面比半导体衬底的表面低300-1500埃。

10. 发明申请

US20070285760A1 Concave and convex micromirrors and methods of making the same 有权
标题翻译：凹凸微镜及其制作方法
公开(公告)号：US20070285760A1
公开(公告)日：2007-12-13
申请号：US11450236
申请日：2006-06-09
申请人： Dah-Chuen Ho , Eugene Chu , Yuh-Haw Chang , Fei-Yun Chen , Michael Wu , Eric Chao
发明人： Dah-Chuen Ho , Eugene Chu , Yuh-Haw Chang , Fei-Yun Chen , Michael Wu , Eric Chao
IPC分类号： G02B26/00
CPC分类号： G02B26/0833 , G02B26/0841
摘要： A method comprising providing a first substrate and forming a first sacrificial layer over the first substrate, the first sacrificial layer comprising a curved surface portion, and forming a curved micromirror by depositing a reflective material over at the curved surface portion.
摘要翻译：一种方法，包括提供第一衬底并在所述第一衬底上形成第一牺牲层，所述第一牺牲层包括弯曲表面部分，以及通过在所述弯曲表面部分上沉积反射材料形成弯曲微镜。

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