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1. 发明授权

US06671644B2 Using clock gating or signal gating to partition a device for fault isolation and diagnostic data collection 失效
公开(公告)号：US06671644B2
公开(公告)日：2003-12-30
申请号：US09930355
申请日：2001-08-15
申请人： Leendert M. Huisman , William V. Huott , Franco Motika , Leah M. Pfeifer Pastel
发明人： Leendert M. Huisman , William V. Huott , Franco Motika , Leah M. Pfeifer Pastel
IPC分类号： G06F1100
CPC分类号： G01R31/31725 , G01R31/318594 , G01R31/31922 , G01R31/31937
摘要： In one aspect, an electronic device that has been partitioned into segments by using clock gating or signal gating is tested. One of the segments that is a source of a failure is identified. Diagnostic procedures are applied to the identified segment to determine a cause of the failure.

2. 发明授权

US07434130B2 Using clock gating or signal gating to partition a device for fault isolation and diagnostic data collection 有权
标题翻译：使用时钟门控或信号门控对设备进行分区以进行故障隔离和诊断数据采集
公开(公告)号：US07434130B2
公开(公告)日：2008-10-07
申请号：US11006274
申请日：2004-12-07
申请人： Leendert M. Huisman , William V. Huott , Franco Motika , Leah M. Pfeifer Pastel
发明人： Leendert M. Huisman , William V. Huott , Franco Motika , Leah M. Pfeifer Pastel
IPC分类号： G01R31/28 , G11C29/00
CPC分类号： G01R31/31725 , G01R31/318594 , G01R31/31922 , G01R31/31937
摘要： In one aspect, an electronic device that has been partitioned into segments by using clock gating or signal gating is tested. One of the segments that is a source of a failure is identified. Diagnostic procedures are applied to the identified segment to determine a cause of the failure.
摘要翻译：在一个方面，测试了通过使用时钟门控或信号门控被划分成段的电子设备。识别出作为故障来源的细分之一。将诊断程序应用于识别的段以确定故障的原因。

3. 发明授权

US06865501B2 Using clock gating or signal gating to partition a device for fault isolation and diagnostic data collection 失效
公开(公告)号：US06865501B2
公开(公告)日：2005-03-08
申请号：US10697365
申请日：2003-10-30
申请人： Leendert M. Huisman , William V. Huott , Franco Motika , Leah M. Pfeifer Pastel
发明人： Leendert M. Huisman , William V. Huott , Franco Motika , Leah M. Pfeifer Pastel
IPC分类号： G01R31/319 , G01R31/3193 , G06F19/00
CPC分类号： G01R31/31725 , G01R31/318594 , G01R31/31922 , G01R31/31937
摘要： In one aspect, an electronic device that has been partitioned into segments by using clock gating or signal gating is tested. One of the segments that is a source of a failure is identified. Diagnostic procedures are applied to the identified segment to determine a cause of the failure.

4. 发明授权

US07313744B2 Methods and apparatus for testing a scan chain to isolate defects 失效
标题翻译：用于测试扫描链以隔离缺陷的方法和装置
公开(公告)号：US07313744B2
公开(公告)日：2007-12-25
申请号：US10708380
申请日：2004-02-27
申请人： Leendert M. Huisman , William V. Huott , Maroun Kassab , Franco Motika
发明人： Leendert M. Huisman , William V. Huott , Maroun Kassab , Franco Motika
IPC分类号： G01R31/28
CPC分类号： G01R31/318533
摘要： Systems, methods and apparatus are provided for isolating a defect in a scan chain. The invention includes modifying a first test mode of a plurality of latches included in a scan chain, operating the latches in the modified first test mode, and operating the plurality of latches included in the scan chain in a second test mode. A portion of the scan chain adjacent and following a stuck-@-0 or stuck-@-1 fault in the scan chain may store and/or output a value complementary to the value on the output of the previous portion of the scan chain due to the fault. Such values may be unloaded from the scan chain and used for diagnosing (e.g., isolating a defect in) the defective scan chain. Numerous other aspects are provided.
摘要翻译：提供了用于隔离扫描链中的缺陷的系统，方法和装置。本发明包括修改包括在扫描链中的多个锁存器的第一测试模式，在修改的第一测试模式下操作锁存器，以及在第二测试模式下操作包括在扫描链中的多个锁存器。扫描链中与扫描链相邻并跟随卡纸 - @ - 0或卡住 - - - 1故障的部分扫描链可以存储和/或输出与扫描链的先前部分的输出值相匹配的值，到了错误。这些值可以从扫描链中卸载并用于诊断（例如，分离缺陷）缺陷扫描链。提供了许多其他方面。

5. 发明授权

US07752514B2 Methods and apparatus for testing a scan chain to isolate defects 失效
标题翻译：用于测试扫描链以隔离缺陷的方法和装置
公开(公告)号：US07752514B2
公开(公告)日：2010-07-06
申请号：US11924597
申请日：2007-10-25
申请人： Leendert M. Huisman , William V. Huott , Maroun Kassab , Franco Motika
发明人： Leendert M. Huisman , William V. Huott , Maroun Kassab , Franco Motika
IPC分类号： G01R31/28
CPC分类号： G01R31/318533
摘要： Systems, methods and apparatus are provided for isolating a defect in a scan chain. The invention includes modifying a first test mode of a plurality of latches included in a scan chain, operating the latches in the modified first test mode, and operating the plurality of latches included in the scan chain in a second test mode. A portion of the scan chain adjacent and following a stuck-@-0 or stuck-@-1 fault in the scan chain may store and/or output a value complementary to the value on the output of the previous portion of the scan chain due to the fault. Such values may be unloaded from the scan chain and used for diagnosing (e.g., isolating a defect in) the defective scan chain. Numerous other aspects are provided.
摘要翻译：提供了用于隔离扫描链中的缺陷的系统，方法和装置。本发明包括修改包括在扫描链中的多个锁存器的第一测试模式，在修改的第一测试模式下操作锁存器，以及在第二测试模式下操作包括在扫描链中的多个锁存器。扫描链中与扫描链相邻并跟随卡纸 - @ - 0或卡住 - - - 1故障的部分扫描链可以存储和/或输出与扫描链的先前部分的输出值相匹配的值，到了错误。这些值可以从扫描链中卸载并用于诊断（例如，分离缺陷）缺陷扫描链。提供了许多其他方面。

6. 发明授权

US07558999B2 Learning based logic diagnosis 有权
标题翻译：基于学习的逻辑诊断
公开(公告)号：US07558999B2
公开(公告)日：2009-07-07
申请号：US10709672
申请日：2004-05-21
申请人： James W. Adkisson , John M. Cohn , Leendert M. Huisman , Maroun Kassab , Leah M. Pfeifer Pastel , David E. Sweenor
发明人： James W. Adkisson , John M. Cohn , Leendert M. Huisman , Maroun Kassab , Leah M. Pfeifer Pastel , David E. Sweenor
IPC分类号： G01R31/28 , G06F11/00 , G11C29/00
CPC分类号： G06F11/2252 , G06F11/261
摘要： A system and method for diagnosing a failure in an electronic device. A disclosed system comprises: a defect table that associates previously studied features with known failures; and a fault isolation system that compares an inputted set of suspected faulty device features with the previously studied features listed in the defect table in order to identify causes of the failure.
摘要翻译：一种用于诊断电子设备故障的系统和方法。所公开的系统包括：将先前研究的特征与已知故障相关联的缺陷表; 以及故障隔离系统，其将输入的可疑故障设备特征集合与缺陷表中列出的先前研究的特征进行比较，以识别故障原因。

7. 发明授权

US07139950B2 Segmented scan chains with dynamic reconfigurations 失效
标题翻译：具有动态重新配置的分段扫描链
公开(公告)号：US07139950B2
公开(公告)日：2006-11-21
申请号：US10707957
申请日：2004-01-28
申请人： Leendert M. Huisman , Leah M. P. Pastel
发明人： Leendert M. Huisman , Leah M. P. Pastel
IPC分类号： G01R31/28 , G06F17/50
CPC分类号： G01R31/318536
摘要： A method is disclosed of diagnosing defects in scan chains by statically and dynamically segmenting and reconfiguring the scan chains. A plurality of serially extending scan chains are partitioned into a plurality of serially arranged equal length segments such that each serially extending scan chain comprises a plurality of serially extending segments. A plurality of multiplexors are positioned between the plurality of segments of each scan chain, and are controlled and utilized to connect each segment of the scan chain to the next serial segment in the same scan chain, or to connect each segment of the scan chain to the next serial segment in a lateral adjacent scan chain. Scan in data patterns are introduced into the plurality of serially extending scan chains. Particular defective segments of the plurality of serially extending scan chains are identified by controlling the multiplexors to connect and shift the data pattern out of each segment of a scan chain serially to the next serial segment in the same scan chain, or to connect and shift the data pattern out of each segment of the scan chain to the next serial segment in an adjacent lateral scan chain, with a sequence of serial shifts and serial-lateral shifts being selected to identify particular defective segments of the plurality of serially extending scan chains.
摘要翻译：公开了通过静态和动态地分割和重新配置扫描链来诊断扫描链中的缺陷的方法。多个串联延伸的扫描链被分割成多个串联布置的等长段，使得每个连续延伸的扫描链包括多个串联延伸段。多个多路复用器位于每个扫描链的多个段之间，并且被控制并用于将扫描链的每个段连接到相同扫描链中的下一个串行段，或将扫描链的每个段连接到横向相邻扫描链中的下一个串行段。扫描数据模式被引入到多个连续延伸的扫描链中。通过控制多路复用器将扫描链的每个段中的数据模式串联连接并移动到同一扫描链中的下一个串行段来识别多个串行延伸扫描链中的特定缺陷段，或者将数据模式连接和移位扫描链的每个段中的数据模式到相邻横向扫描链中的下一个串行段，其中选择串行移位和串行 - 横向移位序列以识别多个连续延伸扫描链中的特定缺陷段。

8. 发明授权

US07089514B2 Defect diagnosis for semiconductor integrated circuits 失效
标题翻译：半导体集成电路缺陷诊断
公开(公告)号：US07089514B2
公开(公告)日：2006-08-08
申请号：US10710879
申请日：2004-08-10
申请人： James W. Adkisson , Greg Bazan , John M. Cohn , Francis Gravel , Leendert M. Huisman , Phillip J. Nigh , Leah M. P. Pastel , Kenneth Rowe , Thomas G. Sopchak , David E. Sweenor
发明人： James W. Adkisson , Greg Bazan , John M. Cohn , Francis Gravel , Leendert M. Huisman , Phillip J. Nigh , Leah M. P. Pastel , Kenneth Rowe , Thomas G. Sopchak , David E. Sweenor
IPC分类号： G06F17/50
CPC分类号： G01R31/31718 , G01R31/318342
摘要： A method for defect diagnosis of semiconductor chip. The method comprises the steps of (a) identifying M design structures and N physical characteristics of the circuit design, wherein M and N are positive integers, wherein each design structure of the M design structures is testable as to pass or fail, and wherein each physical characteristic of the N physical characteristics is present in at least one design structure of the M design structures; (b) for each design structure of the M design structures of the circuit design, determining a fail rate and determining whether the fail rate is high or low; and (c) if every design structure of the M design structures in which a physical characteristic of the N physical characteristics is present has a high fail rate, then flagging the physical characteristic as being likely to contain at least a defect.
摘要翻译：一种半导体芯片缺陷诊断方法。该方法包括以下步骤：（a）识别电路设计的M个设计结构和N个物理特性，其中M和N是正整数，其中M个设计结构的每个设计结构可以通过或失败，并且其中每个 N物理特性的物理特性存在于M设计结构的至少一个设计结构中; （b）对于电路设计的M设计结构的每个设计结构，确定故障率并确定故障率是高还是低; 和（c）如果存在N个物理特性的物理特性的M设计结构的每个设计结构具有高故障率，则将物理特性标记为可能至少包含缺陷。

9. 发明授权

US06931580B1 Rapid fail analysis of embedded objects 失效
标题翻译：嵌入式对象的快速故障分析
公开(公告)号：US06931580B1
公开(公告)日：2005-08-16
申请号：US09524254
申请日：2000-03-13
申请人： Kevin J. Barcomb , Leendert M. Huisman , Mark F. Olive , Kevin C. Quandt
发明人： Kevin J. Barcomb , Leendert M. Huisman , Mark F. Olive , Kevin C. Quandt
IPC分类号： G06F11/00 , G11C29/00 , G11C29/56
CPC分类号： G11C29/006 , G11C29/56 , G11C29/56008 , G11C2029/0401
摘要： A method for analyzing test data for objects on an IC or a wafer is provided. The test data is linked to available layout information about the object under test. Certain objects are selected based on the test data. A representation of the selected objects is placed on a map of the IC or on a map of the wafer. The representation should correspond to the physical location of the object on the IC or wafer. Preferably, the representation comprises one or more polygons that enclose all devices that make up the object.
摘要翻译：提供了用于分析IC或晶片上的对象的测试数据的方法。测试数据链接到有关被测对象的可用布局信息。某些对象是根据测试数据进行选择的。所选对象的表示被放置在IC的地图上或晶片的地图上。该表示应对应于IC或晶片上物体的物理位置。优选地，该表示包括包围构成对象的所有设备的一个或多个多边形。

10. 发明授权

US4726023A Determination of testability of combined logic end memory by ignoring memory 失效
标题翻译：通过忽略内存来确定组合逻辑终端内存的可测试性
公开(公告)号：US4726023A
公开(公告)日：1988-02-16
申请号：US862950
申请日：1986-05-14
申请人： John L. Carter , Leendert M. Huisman , Thomas W. Williams
发明人： John L. Carter , Leendert M. Huisman , Thomas W. Williams
IPC分类号： G06F11/26 , G11C29/54 , G01R31/28
CPC分类号： G06F11/26 , G11C29/54
摘要： A method of bounding, from above and below, the probability of uncovering a fault in a logic portion of an integrated circuit having embedded memory. The circuit must be designed according to a specified set of design rules. Then one or more probabilities of fault exposure is calculated for a modified system with the memory portion removed, with its inputs directly connected to its outputs. This probability can be related, by provided relations, to upper and lower bounds of the fault exposure in the unmodified system. The relationships rely upon how the logic portions process given test vectors to control the unremoved memory portion.
摘要翻译：从上方和下方界定揭示具有嵌入式存储器的集成电路的逻辑部分中的故障的概率的方法。电路必须按照一组规定设计。然后针对已删除存储器部分的修改系统计算出一个或多个故障曝光概率，其输入直接连接到其输出。这种概率可以通过提供的关系与未修改系统中的故障暴露的上限和下限相关联。这些关系依赖于逻辑部分如何处理给定的测试向量来控制未移动的存储器部分。

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